Dual loop PLL with secondary loop to achieve 50% duty cycle

Details Dual loop PLL with secondary loop to achieve 50% duty cycle Dual loop PLL with secondary loop to achieve 50% duty cycle

1996-12-09

1999-06-15

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327175, 327298, 331 34, H03K 3017

Patent

active

059125748

ABSTRACT:
A phased lock loop (PLL) clock circuit generates a clock signal at 1x the desired clock frequency while maintaining substantially a 50% duty cycle. A first loop provides a feedback signal to maintain clock frequency, while a second loop provides a feedback signal and controls duty cycle. Two clock signals from a ring oscillator are fed to a level shifter, where each clock signal triggers a respective rising or trailing edge of the output clock signal. The level shifter is provided with a delay for controlling timing of the trailing edge of the output clock signal. The output clock signal is fed to a equi-current buffer where a charge pump, driven by the output clock signal, charges and discharges a capacitor in proportion to the duty cycle of the output clock signal, producing a feedback control voltage. The feedback control voltage is applied to the delay of the level shifter to maintain a substantially 50% duty cycle. The clock circuit of the present invention has improved power supply noise immunity and control voltage headroom for operation at different design frequencies.

REFERENCES:
patent: 4959557 (1990-09-01), Miller
patent: 5057702 (1991-10-01), Kitagawa et al.
patent: 5345186 (1994-09-01), Lesmeister
patent: 5371425 (1994-12-01), Rogers
patent: 5477180 (1995-12-01), Chen
patent: 5572158 (1996-11-01), Lee et al.

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