Dual loop PLL, and multiplication clock generator using dual...

Details Dual loop PLL, and multiplication clock generator using dual... Dual loop PLL, and multiplication clock generator using dual...

2008-01-29

2008-01-29

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S011000, C331S025000, C331S044000, C331S175000, C327S157000

Reexamination Certificate

active

07323942

ABSTRACT:
To provide dual loop PLLs capable of reducing the lock-up time in the initial start-up, and multiplication clock generators contributing to reduction of the power dissipation. The dual loop PLL comprises a dual loop PLL having a phase comparison loop having a phase comparator1for comparing phases, and a frequency comparison loop having a frequency comparator7for comparing frequencies, wherein the frequency comparator7carries out frequency comparison using an input signal inputted from a calibration clock line CLcal18, the input signal being different from a reference clock signal inputted from an external reference clock line CLex11, the reference clock signal being used for a phase comparator1. Moreover, multiplication clock generators are configured using the dual loop PLL.

REFERENCES:
patent: 6150886 (2000-11-01), Shimomura
patent: 6466096 (2002-10-01), DeVito
patent: 7065017 (2006-06-01), Nishida
patent: 2004/0196107 (2004-10-01), Sogawa et al.
patent: 2005/0137816 (2005-06-01), Chuang et al.
patent: 52-060052 (1977-05-01), None
patent: 2000-307420 (2000-11-01), None
patent: 2001-136065 (2001-05-01), None
patent: 2002-352517 (2002-12-01), None
patent: 2003-298417 (2003-10-01), None
patent: 03/090358 (2003-10-01), None
Yi-Cheng Chang and Edwin W. Greeneich, “Monolithic phase-locked loop circuit with coarse-steering acquisition aid,” Circuit and Systems, 1999, 42nd Midwest Symposium on, vol. 1, 1999, pp. 283-286.
English language Abstract of JP 2001-136065.
English language Abstract of JP 52-060052.
English language Abstract of JP 2002-352517.
English language Abstract of JP 2003-298417.
English language Abstract of JP 2000-307420.

Affiliated with

Also associated with

Rating

Dual loop PLL, and multiplication clock generator using dual... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual loop PLL, and multiplication clock generator using dual..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual loop PLL, and multiplication clock generator using dual... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2809809