Dual loop phase locked loop

Details Dual loop phase locked loop Dual loop phase locked loop

2006-04-04

2006-04-04

Nguyen, Linh My (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C327S141000

Reexamination Certificate

active

07023284

ABSTRACT:
In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit30of an up/down counter8receives an UP signal from a frequency comparator7, the input control circuit30outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit30receives a DOWN signal from the frequency comparator7, the input control circuit30outputs a negative value of a ½ of the previous addition/subtraction result value. A register33stores a count value. The adder31adds the output of the input control circuit30to the output of the register33. Thus, the up/down counter8increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.

REFERENCES:
patent: 5506875 (1996-04-01), Nuckolls et al.
patent: 6504438 (2003-01-01), Chang et al.
patent: 6650720 (2003-11-01), Grung et al.
patent: 09-246963 (1997-09-01), None
patent: 2001-332969 (2001-11-01), None
Yi-Cheng Chang et al., “ Monolithic Phase-Locked Loop Circuits with Coarse-Steering Acquisition Aid”, Department of Electrical Engineering Arizona State University, Tempe, AZ 85287, 1999 IEEE, pp. 283-286.

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