Dual loop delay-locked loop

Details Dual loop delay-locked loop Dual loop delay-locked loop

1998-01-15

1999-10-19

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327149, 327161, 327153, 327276, H03K 513

Patent

active

059695528

ABSTRACT:
A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop and a phase acquisition loop. The frequency acquisition loop delays the reference clock to produce an intermediate clock which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock to produce a local clock synchronized to the reference clock.

REFERENCES:
patent: 5101117 (1992-03-01), Johnson
patent: 5109394 (1992-04-01), Hjerpe et al.
patent: 5552726 (1996-09-01), Wichman
patent: 5744991 (1998-04-01), Jefferson

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