Dual loop clock recovery circuit

Details Dual loop clock recovery circuit Dual loop clock recovery circuit

2009-06-11

2011-10-11

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Systems using alternating or pulsating current

Angle modulation

C375S372000, C708S003000

Reexamination Certificate

active

08036300

ABSTRACT:
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

REFERENCES:
patent: 5258933 (1993-11-01), Johnson et al.
patent: 5341249 (1994-08-01), Abbott et al.
patent: 5552942 (1996-09-01), Ziperovich et al.
patent: 5867544 (1999-02-01), Taniguchi
patent: 5937020 (1999-08-01), Hase et al.
patent: 5990714 (1999-11-01), Takahashi et al.
patent: 6191906 (2001-02-01), Buch
patent: 6580304 (2003-06-01), Rieven
patent: 6617936 (2003-09-01), Dally et al.
patent: RE38482 (2004-03-01), Leung et al.
patent: 6861916 (2005-03-01), Dally et al.
patent: 6914465 (2005-07-01), Kiyose et al.
patent: 6950956 (2005-09-01), Zerbe et al.
patent: 2002/0037065 (2002-03-01), Nakamura
patent: 2002/0075980 (2002-06-01), Tang et al.
patent: 2002/0105386 (2002-08-01), Shastri
patent: 2003/0025539 (2003-02-01), Fiscus
patent: 2003/0035502 (2003-02-01), Boerker
patent: 2003/0103591 (2003-06-01), Noguchi
patent: 2004/0052323 (2004-03-01), Zhang
patent: 2004/0141577 (2004-07-01), Brunn et al.
patent: 2004/0202266 (2004-10-01), Gregorius et al.
patent: 2004/0223575 (2004-11-01), Meltzer et al.
patent: 2005/0231249 (2005-10-01), Tani
“Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design,” Behzad Razavi, ed., IEEE Press (1994), pp. 33-35.
Gursoy, Zafer Ozgur (ST Microelectronics), and Yusuf Leblebici (Swiss Federal Inst. Of Tech.—Lausanne), “Design and Realization of a 2.4 Gbps—3.2 Gbps Clock and Data Recovery Circuit Using Deep-Submicron Digital CMOS Technology.”
Sidiropoulos, Stefanos and Mark Horowitz, “SA20.2: A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range,” Center for Integrated Systems, Stanford Univ., Stanford, CA, mos.stanford.edu.\papers\ss—1sscl—97.pdf.
Kim, Dong-Hee and Jin-Ku Kang, “A 1.0-Gbps Clock and Data Recovery Circuit with Two-XOR Phase-Frequency Detector,” Dept. of Electrical and Computer Engineering , Inha Univ., Inchon, Korea.
Hogge, Jr., Charles R., “A Self Correcting Clock Recovery Circuit,” J. of Lightwave Tech., vol. LT-3, No. 6, Dec. 1985.
Song, Yeo-San and Jin-Ku Kang, “A Delay Locked Loop Circuit With Mixed-Mode Tuning,” Dept. of Electrical and Computer Engineering, Inha Univ., Inchon, Korea.
Lee, Haechang, Chi Ho Yue, Samuel Palermo, Kenneth W. Mai, and Mark Horowitz, “Burst Mode Package Receiver using a Second Order DLL,” Center for Integrated Systems, Stanford Univ., Stanford, CA.
Lee, Thomas H., “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop,” IEEE J. of Solid-State Circuits, vol. 27, No. 12, Dec. 1992.
Wong, Koon-Lun Jackie, Hamid Hatamkhani, and Mozhgan Mansuri, “A 27-mW 3.6-Gb/s I/O Transceiver,” IEEE J. of Solid-State Circuits, vol. 39, No. 4, Apr. 2004.
Toifl, Thomas, Christian Menolfi, Peter Buchmann, Marcel Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin Schmatz, and Jonas Weiss, “0.94ps-rms-Jitter 0.016mm22.5GHz Multi-Phase Generator PLL with 360° Digitally Programmable Phase Shift for 10Gb/s Serial Links,” 2005 IEEE Int'l Solid-State Circuits Conference.
Emami-Neyestanak, Azita, Samuel Palermo, Hae-Chang Lee and Mark Horowitz, “CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects,” Computer Systems Lab., Stanford, CA.
Larsson, Patrick, “A 2-600-MHz CMOS Clock Recovery PLL with Low-VddCapability,” IEEE J. of Solid-State Circuits, vol. 34, No. 12, Dec. 1999.
Kim, Jaeha and Mark A. Horowitz, “Adaptive Supply Serial Links With Sub-1-V Operation and Per-Pin Clock Recovery,” IEEE J. of Solid-State Circuits, vol. 37, No. 11, Nov. 2002.
Song, Yeo-San et al., A Delay Locked Loop Circuit with Mixed Mode Phase Tuning Technique, IEICE Trans. Fundaments, vol. E83-A, No. 9, Sep. 2000.
Gursoy, Zafer Ozgur, and Yusuf Leblebici, “Design and Realization of a 2.4 Gbps—3.2 Gbps Clock and Data Recovery Circuit Using Deep-Submicron Digital CMOS Technology.”
A fully integrated 43.2-Gb/s clock and data recovery and 1:4 DEMUX IC in InP HBT technology Nielsen, S., Yen, J.C.; Srivastava, N.K.; Rogers, J.E.; Case, M.G.; Thiagarajah, R.; Solid-Sate Circuits, IEEE Journal of, vol. 38, Issue 12, Dec. 2003, pp. 2341-2346.

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