Dual-line type charge transfer device

Details Dual-line type charge transfer device Dual-line type charge transfer device

1999-04-26

2002-08-27

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S221000, C257S234000, C257S241000

Reexamination Certificate

active

06441409

ABSTRACT:

This application is based on Japanese patent applications No. 10-135410 filed on May 18, 1998, and No. 10-135411 filed on May 18, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a solid-state image pickup device, more particularly to a solid-state image pickup device having a dual-line type horizontal charge transfer device.
b) Description of the Related Art
FIG. 2
is a diagram showing the structure of a solid-state image pickup device
1
having a dual-line type horizontal charge transfer device
5
.
A pixel array
2
comprises a plurality of photo diodes (photoelectric converter elements)
3
arranged in a flat matrix form, and a plurality of vertical charge transfer devices
4
. The photo diodes
3
convert received lights into charges, and each of the photo diodes
3
corresponds to one of the pixels which form a two-dimensional image. The photo diodes
3
transfer the charges to the plurality of vertical charge transfer devices
4
which transfer the charges in the vertical direction.
The dual-line type horizontal charge transfer device
5
comprises a first horizontal charge transfer device
5
a
and a second horizontal charge transfer device
5
b
. The vertical charge transfer devices
4
and the horizontal charge transfer devices
5
a
and
5
b
comprise charge coupled devices (CCD). The charges in the vertical charge transfer devices
4
are transferred downward in the vertical direction toward one of the first horizontal charge transfer device
5
a
or the second horizontal charge transfer device
5
b
. The first and second horizontal charge transfer devices
5
a
and
5
b
horizontally transfer the charges leftward.
The first horizontal charge transfer device
5
a
transfers the charges to a first amplifier
6
a
. The first amplifier
6
a
amplifies the received charges and outputs the amplified charges. The second horizontal charge transfer device
5
b
transfers the charges to a second amplifier
6
b
. The second amplifier
6
b
amplifies the received charges and output the amplified charges.
A solid-state image pickup device used in, for example, a high definition television (HDTV), which is designed for high resolution image capturing is required to transfer charges quickly because it has a large number of photo diodes (pixels). In such a case, the solid-state image pickup device
1
having the dual-line type horizontal charge transfer device
5
is used in order to improve the charge transfer efficiency in the CCD and equalize amplification sensitivity.
The structure of a boundary area
7
between the first and second horizontal charge transfer devices
5
a
and
5
b
will now be described.
An upper diagram of
FIG. 3
is a plan view showing the boundary area
7
. The portrait direction of
FIG. 3
corresponds to the landscape direction of
FIG. 2. A
shift gate
12
is disposed between the first and second horizontal charge transfer devices
5
a
and
5
b
. Graphs shown in middle and lower sections of
FIG. 3
show potential energy variation in the boundary area
7
wherein the horizontal axes indicate positions in the boundary area
7
and the vertical axes indicate the potential energy variation against the charges (electrons).
Potential energy waveform S
1
shown in the middle graph of
FIG. 3
represents potential energy variation when the shift gate
12
is closed because a gate signal is not applied thereto. Since the shift gate
12
is closed, the charges in the first horizontal charge transfer device
5
a
which are transferred from the vertical charge transfer devices
4
(
FIG. 2
) stay in the first horizontal charge transfer device
5
a.
Potential energy waveform S
2
shown in the lower graph of
FIG. 3
represents potential energy variation when the shift gate
12
is open after the gate signal is applied thereto. When the gate signal is applied to the shift gate
12
, potential energy of the second horizontal charge transfer device
5
b
decreases because the second horizontal charge transfer device
5
b
is biased. Since the shift gate
12
is open, the charges in the first horizontal charge transfer device
5
a
which are transferred from the vertical charge transfer devices
4
(
FIG. 2
) are further transferred in the vertical direction (the landscape direction in
FIG. 3
) toward the second horizontal charge transfer device
5
b
. The transferred charges
13
will stay in the second horizontal charge transfer device
5
b
after the shift gate
12
is closed.
That is, the charges in the vertical charge transfer devices are controlled so as to be transferred one of the first and second horizontal charge transfer device
5
a
and
5
b
by switching the shift gate
12
.
An upper diagram in
FIG. 4
is a plan view for explaining a transfer operation of the charges
11
in the first horizontal charge transfer device
5
a.
The horizontal charge transfer device
5
a
comprises groups each consisting of a first well region W
1
, a first barrier region B
1
, a second well region W
2
and a second barrier region B
2
. A predetermined number of the groups are arranged in the horizontal direction. A drive signal H&phgr;
1
is applied to the first well region W
1
and the first barrier region B
1
. A drive signal H&phgr;
2
is applied to the second well region W
2
and the second barrier region B
2
. That is, the horizontal charge transfer device
5
a
is driven by the dual-phase drive signals H&phgr;
1
and H&phgr;
2
.
Graphs shown in middle and lower sections of
FIG. 4
represent the potential energy variation in the horizontal charge transfer device
5
a
wherein the horizontal axis indicates positions in the horizontal charge transfer device
5
a
and the vertical axis indicates the potential energy variation.
Potential energy waveform S
1
shown in the middle graph of
FIG. 4
represents potential energy variation when the drive signals H&phgr;
1
and H&phgr;
2
are 0V. Effective dopant concentration is adjusted so that the potential energy of the well regions W
1
and W
2
is lower than that of the barrier regions B
1
and B
2
. For example, the well regions W
1
and W
2
are n-type regions having high dopant concentration and the barrier regions B
1
and B
2
are n-type regions having low dopant concentration. The well regions W
1
and W
2
show almost the same potential energy level. The barrier regions B
1
and B
2
also show almost the same potential energy level.
Potential energy waveform S
2
shown in the lower graph of
FIG. 4
represents potential energy variation when the drive signal H&phgr;
1
is 5V while the drive signal H&phgr;
2
is 0V. According to the graph, potential energy gradient appears in the horizontal charge transfer device
5
a
. That is, the potential energy level gradually decreases from higher potential energy region B
2
to lower potential energy region W
1
. In the horizontal charge transfer device
5
a
, the charges
11
are transferred leftward in the horizontal direction in accordance with the potential gradient.
FIGS. 5A
to
5
D are cross sectional views showing a device for explaining steps of manufacturing a horizontal charge transfer device (charge coupled device) in the prior art.
As shown in
FIG. 5A
, n-type dopant
23
is added to a p-type silicon region
21
of a silicon substrate by ion implantation. As a result, an n-type silicon region
22
is formed on the p-type silicon region
21
.
Then, a silicon oxide layer
24
is formed on the n-type silicon region
22
as shown in
FIG. 5B
, and then patterned first poly gates
25
made of amorphous silicon are formed on the silicon oxide layer
24
. The first poly gates
25
work as electrodes for the well regions W
1
and W
2
.
Then, p-type dopant
27
is added to the substrate by ion implantation as shown in FIG.
5
C. During the doping, the first poly gates
25
work as a mask. As a result, p-type silicon regions
26
are formed on exposed surfaces of the n-type silicon regions
22
which are unmasked by the first poly gates
25
. The p-type sil

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