Dual-limit current-limiting battery-feed circuit for a digital l

Telephonic communications – Subscriber line or transmission line interface – Network interface device

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Details

379399, 379402, 379404, 379412, 361 93, H04M 1900

Patent

active

060699507

ABSTRACT:
A current-limiting circuit (110) of a battery-feed circuit (FIG. 1) for a digital telecommunications line (T,R) provides a low start-up current limit (I3) when power is initially applied to the digital line. It automatically and gradually changes (40) to a high current limit (I1) as the load on the line is charged. When the load is fully charged, the circuit provides a low impedance to the line. Upon occurrence of a fault, the circuit switches back to the initial low current-limit state. The circuit comprises a feed transistor (Q1, Q11), a control transistor (Q2, Q12), and a high-impedance resistive circuit (R1-R4, R15). The feed transistor limits (403) current flowing to the R lead of the line to the high limit when the voltage across the feed transistor is low (0-V2) and the feed transistor is saturated. The control transistor partially turns off the feed transistor when the voltage is intermediate (V2-V4) causing the feed transistor to provide (402) an intermediate current that is inversely proportional to the voltage across the feed transistor. When the voltage across the feed transistor is high (V4), the control transistor turns the feed transistor off and the resistive circuit supplies (401) the low current to the R lead.

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Designer's.TM. Data Sheet SMARTDISCRETES.TM. Internally Clamped, Current Limited N-Channel Logic Level Power MOSFET, Motorola, Inc. 1996, Document MLP2N06CL/D, pp. 1-6.
TMOS Power MOSFET Transistor Device Data, Motorola, Inc., 1994, Document DL135/D REV5, pp. 2-11-1-2-11-4.

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