Dual-level voltage shifters for low leakage power

Details Dual-level voltage shifters for low leakage power Dual-level voltage shifters for low leakage power

2001-02-08

2002-06-04

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S208000, C327S219000, C326S081000, C326S068000

Reexamination Certificate

active

06400206

ABSTRACT:

FIELD
The present invention relates generally to voltage shifters, and more specifically to dual-level voltage shifters.
BACKGROUND
One of the most challenging problems confronting the designer in deep submicron circuits in today's technological society is leakage power which has increasingly become accountable for a significant portion of the total power consumption of such devices. Recent circuit techniques to reduce the leakage power in circuits have employed higher supply voltage to the circuit in an attempt to drive a leakage control device. One common type of leakage reduction technique comprises a sleep transistor whose gate node is driven by the additional supply voltages. A second type of leakage reduction technique changes the application circuit's body bias using the additional supply voltages. To switch between the standby and active modes, the sleep transistor's gate bias in the case of the first type of leakage reduction or the body bias of the circuit in the case of the second type of leakage reduction need to be switched between different voltage levels. This is accomplished through the use of a voltage shifter. Traditional voltage shifters, however, typically flow a significant amount of static current or support only single level voltage shifting.
For example,
FIG. 1
shows a voltage shifter
100
with static current flowing. Voltage shifter
100
comprises a series connection of p-type transistor
102
and n-type transistor
104
in series between voltage V
cc
and ground. The gates of transistors
102
and
104
are connected to each other. Transistors
106
and
108
are connected in series between V
pp
and V
nn
, where V
pp
=V
cc
+&Dgr;V and V
nn
=−&Dgr;V. The gates of transistors
106
and
108
connected to each other and to a node
110
between transistors
102
and
104
. An input voltage V
in
is supplied to the gates of transistors
102
and
104
, and an output is generated from between transistors
106
and
108
. V
in
varies from a logical one (V
cc
) to a logical zero (0V). V
out
varies from V
cc
+&Dgr;V to V
cc
−&Dgr;V.
When V
in
is set to V
cc
transistor
104
is on and transistor
102
is off, but the ground voltage at node
110
is insufficient to completely shut off transistor
106
, and a static current flows in path
112
. When V
in
is set to 0V, transistor
104
is off and transistor
102
is on, but the voltage V
cc
at node
110
is insufficient to completely shut off transistor
108
, and a static current flows in path
114
. Shifter
100
cannot be used for low power circuits.
Another example of a prior art voltage shifter
200
is shown in FIG.
2
. Voltage shifter
200
comprises p-type transistor
202
and n-type transistor
204
connected in series between voltage V
pp
and V
nn
, which is ground, and p-type transistor
206
and n-type transistor
208
also connected in series between V
pp
and V
nn
(ground). An input voltage V
in
is connected to the gate of transistor
204
, and through inverter
210
to the gate of transistor
208
. The gate of transistor
202
is connected at an output node defined between transistors
206
and
208
. The gate of transistor
206
is connected between transistors
202
and
204
.
In this configuration, when V
in
is equal to V
cc
, transistors
204
and
206
are on, and transistors
202
and
208
are off, and V
out
is pulled to V
pp
, which equals V
cc
+&Dgr;V, through transistor
206
. When V
in
is set to 0V, transistors
202
and
208
turn on, and transistors
204
and
206
turn off. In this instance, V
out
is pulled to V
nn
(ground) through transistor
208
. In this single level voltage shifter, no static current flows. However, the circuit
200
is only a single level voltage shifter. If V
nn
is set to −&Dgr;V to achieve dual-level voltage shifting, transistors
204
and
208
cannot be fully shut off and static current will flow. Shifter
200
cannot be used for leakage reduction.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the resent specification, there is a need in the art for a dual-level voltage shifter with no static current flow, and which is capable of use with low power circuits.
SUMMARY
In some embodiments, the invention includes first and second transistors connected in series, and third and fourth transistors connected in series, each series connection between a first potential and a second potential. The gates of the first and third transistors are connected to complementary inputs. Fifth and sixth transistors are also connected in series, and seventh and eighth transistors are also connected in series, each series connection between a third potential and the second potential. The gates of the fourth and sixth transistors are connected to a first node between the first and second transistors, and the gates of the second and eighth transistors are connected to a second node between the third and fourth transistors.
In other embodiments, a level shifter includes a first transistor configured as a diode, a first CMOS inverter, and a second transistor configured as a diode, the first transistor, first inverter, and second transistor connected in series between a first voltage connection and a second voltage connection. Further, a second inverter and a third inverter are connected in parallel between a third voltage connection and a fourth voltage connection. The second and the third inverters are cross coupled, and the output of the first inverter and the input of the second inverter are operatively coupled together. A pass gate is in the feedback loop between the second and the third inverters.
Other embodiments are described and claimed.


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