Dual level scheduling of processes to multiple parallel regions

Details Dual level scheduling of processes to multiple parallel regions Dual level scheduling of processes to multiple parallel regions

1992-11-09

1994-08-16

Shaw, Gareth D.

Boots, shoes, and leggings

3642303, 3642457, 364246, 3642814, 3642816, 3642817, 3642818, 364DIG1, G06F 946

Patent

active

053394151

ABSTRACT:
On a tightly coupled multiprocessor computer system, the multiple parallel regions of a multithreaded applications program can execute simultaneously as multiple threads on a plurality of processors. Furthermore, a plurality of multithreaded programs may run simultaneously. The current invention uses an efficient system to schedule and reschedule processors to run these multiple threads. Scheduling is integrated at two levels: at the first level, processors are assigned processes. At the next level, processes are assigned threads. Increased efficiency is achieved by this integration and also by the formation of processes with destructible context. It makes use of shared storage to indicate the process request level and the control state for each parallel region.

REFERENCES:
patent: 4631674 (1986-12-01), Blandy
patent: 4636942 (1987-01-01), Chen et al.
patent: 4829422 (1989-05-01), Morton et al.
patent: 5050070 (1991-09-01), Chastain et al.
patent: 5179702 (1993-01-01), Spix et al.
H. Jacobs, "User-Tunable Multiple Processor Scheduler", Proc. Usenix Technical Conference, pp. 183-192 (1986).
M. Chastain et al., "The Convex C240 Architecture", Proc. Supercomputing Conf., pp. 320-329 (1988).

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