Dual level polysilicon single transistor-capacitor memory array

Details Dual level polysilicon single transistor-capacitor memory array Dual level polysilicon single transistor-capacitor memory array

1985-01-24

1989-12-12

Carroll, J.

357 41, 357 45, 357 59, H01L 2978, H01L 2702, H01L 2710, H01L 2904

Patent

active

048871354

ABSTRACT:
A self-aligned one transistor-capacitor memory cell is provided which uses an n-channel MOS transistor having separate drain and source regions with a first level polysilicon conductor coupled to the top plate of the capacitor and separate second level polysilicon conductors coupled to the gate and drain of the transistor. A reduction in a dimension of the memory cell is acheived compared to a similar memory cell which uses only one level of conductors.

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