Dual level error detection and correction employing data subsets

Details Dual level error detection and correction employing data subsets Dual level error detection and correction employing data subsets

1995-03-09

1996-12-03

Beausoliel, Jr., Robert W.

Excavating

371 491, 371 402, G11C 2900

Patent

active

055815677

ABSTRACT:
A memory system that provides extra data bits without utilizing storage capacity. A first data word is fetched from memory and corrected to remove any single-bit errors. A second data word (which is a subset of the first data word as corrected) is then fetched, and new data correction bits (parity or ECC check bits) is generated for the second data word. Both the second data word and the newly-generated data correction bits are output. This structure amortizes the expense of in-system data correction over a greater data output, and over a smaller storage capacity relative to the data output.

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