Dual leadframe package

Details Dual leadframe package Dual leadframe package

1999-05-17

2001-04-10

Lee, Eddie C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S675000, C257S796000, C257S705000, C257S712000

Reexamination Certificate

active

06215176

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88107215, filed May 4, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package. More particularly, the present invention relates to a dual leadframe package.
2. Description of the Related Art
As chip integration increases, various semiconductor packages are used, such as a chip scale package or a multi-chip module, for example. However, a leadframe is usually used for packaging a low pin count chip such as a high-voltage device.
FIG. 1
is a schematic, cross-sectional view of a conventional low pin count semiconductor package.
Referring to
FIG. 1
, a chip
12
is attached to a bonding pad
10
and coupled to a lead
18
through a wire
14
formed by wire bonding. The chip
12
, the wire
14
, the bonding pad
10
and a portion of the lead
18
are sealed by a packaging material
16
. The packaging material
16
fixes the relative position of the chip
12
, the bonding pad
10
, the wire
14
and the lead
18
and protects the chip
12
. A portion of the lead
18
exposed is bent downward for coupling to a printed circuit board. Additionally, the lead
18
can be formed in a gull wing shape to couple to the printed circuit board through a surface mount technique.
In the conventional packaging process, many steps are needed and many kinds of machines are needed to perform the steps. Furthermore, it is time-consuming to perform the wire bonding process. The manufacturing time and the manufacturing cost are high. It is difficult to increase throughput.
The signal transmitting path including the lead and the wire is long, so that impedance may increase, and signal decay and signal delay may occur. The package structure properties do not satisfy the requirement of the chip. For example, in 0.4 &mgr;m MOS, the resistance of the chip is 0.2 m&OHgr;-cm. However, the resistance of the chip scale package is 20 m&OHgr;-cm, so that the performance of the chip is seriously affected. Moreover, the volume of the package is large. The large volume restricts the application of the chip.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a dual leadframe package, for which package the volume is small and the signal transmitting path is short.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a dual leadframe package. A chip including a first surface and a second surface is provided. A gate and a first source/drain region are located on the first surface, and a second source/drain region is located on the second surface. A first lead including a first innerlead and a first outerlead and a second lead including a second innerlead and a second outerlead are provided. The first innerlead is coupled to the first source/drain region, and the second innerlead is coupled to the gate. A conductive plate including a top surface and a bottom surface is provided, and the top surface is coupled to the second source/drain region. A packaging material seals the chip, the first innerlead, the outerlead and a portion of the conductive plate. The bottom surface, the first outerlead and the second outerlead are exposed.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating a dual leadframe package. The method includes the following steps. A chip having a first surface and a second surface is provided. A gate and a first source/drain region are located on the first surface, and a second source/drain region is located on the second surface. A first leadframe including a dam bar, a first lead and a second lead, and a second leadframe including a conductive plate are provided. The first lead and the second lead are fixed on the first leadframe through the dam bar. The conductive plate is supported by the supporting bar. The first leadframe is placed on the first surface, the first lead is coupled to the first source/drain region and the second lead is coupled to the gate. The second leadframe is placed on the second surface and the conductive plate is coupled to second source/drain region. The chip, the first lead, the second lead and a portion of the conductive plate are sealed by a packaging material.
In the invention, the lead and the conductive plate are directly coupled to the chip, so the signal transmitting path is obviously reduced and the resistance of the package is also reduced. Furthermore, the conductive plate serves as a heat slug to help dissipate heat generated by operating the chip.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4984059 (1991-01-01), Kubota et al.
patent: 5606199 (1997-02-01), Yoshigai
patent: 5625226 (1997-04-01), Kinzer
patent: 5637915 (1997-06-01), Sato et al.
patent: 5796162 (1998-08-01), Huang et al.
patent: 5844310 (1998-12-01), Okikawa et al.
patent: 6072228 (2000-06-01), Hinkle et al.

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