Dual layer surface gate JFET having enhanced gate-channel breakd

Details Dual layer surface gate JFET having enhanced gate-channel breakd Dual layer surface gate JFET having enhanced gate-channel breakd

1989-10-20

1991-04-16

Mintel, William

357 52, 357 49, 357 20, H01L 2980

Patent

active

050087193

ABSTRACT:
Radiation insensitivity and breakdown voltage characteristics of a dual region top gate JFET are improved by a top gate structure in which the entirety of the lower concentration region of the top gate is separated from the oxide/silicon interface by the top surface high impurity concentration region. The dual region top gate extends from the substrate/insulator interface to a channel region beneath the top surface of the JFET substrate and extends laterally to bridge the source and drain regions. The lateral extent of the dual region top gate may be delimited by barrier regions, respectively separating the top gate regions from the source and drain regions. The barrier regions extend from the substrate/oxide interface to the channel and may comprise dielectric material or a combination of dielectric material and doped semiconductor material.

REFERENCES:
patent: 4496983 (1985-01-01), Dunkley et al.
patent: 4816880 (1989-03-01), Muro
patent: 4912053 (1990-03-01), Schrantz
Roach et al., "Sidegating in GaAs Current Limiters," IEEE Transactions on Electron Devices, vol. ED-34, No. 2, Feb. 1987, pp. 181-184.

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