Dual-instruction-set architecture CPU with hidden software emula

Details Dual-instruction-set architecture CPU with hidden software emula Dual-instruction-set architecture CPU with hidden software emula

1994-01-11

1998-07-14

Lall, Parshotam S.

395500, 395570, G06F 9455

Patent

active

057817502

ABSTRACT:
A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computer) code. Three modes of operation are provided: CISC mode, RISC mode, both called user modes, and emulation mode. Emulation mode is entered upon reset, and performs various system checks and memory allocation. A special emulation driver is loaded into a portion of main memory set aside at reset. Software routines to emulate the more complex instructions of the CISC architecture using RISC instructions are also loaded into the emulation memory. A TLB is enabled, and translation tables and drivers are set up in the emulation memory. All TLB misses, even in the user modes, will cause entry to a translator driver in emulation mode. Since the TLB is always enabled for the user modes, and all misses are handled by the emulation code, the emulation code can set aside a portion of memory for itself and insure that the user programs never have access to the emulation memory. Thus the programs, including operating systems, in CISC or RISC mode are unaware of emulation memory or even the existence of emulation mode.

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