Dual input switched capacitor gain stage

Details Dual input switched capacitor gain stage Dual input switched capacitor gain stage

2000-09-12

2002-03-26

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S141000, C327S096000, C327S553000

Reexamination Certificate

active

06362770

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to switched capacitor gain stages, such as are used in pipelined analog digital converters and, in particular, to a gain stage providing dual input capabilities.
BACKGROUND OF THE INVENTION
Switched capacitor gain stages provide precisely defined gains determined by a ratio in values between closely matched capacitors, typically on a single integrated circuit.
In one type of capacitor gain stage, a pair of capacitors is charged in parallel across an input voltage and a ground reference. The capacitor terminals that are attached to the ground reference are then moved to the inverting input of an operational amplifier while one of the capacitor terminals previously attached to the input voltage is moved to the output of the amplifier and the other capacitor terminal previously attached to the input voltage is attached to a reference voltage. When the capacitors have the same value, the output of the amplifier will then be twice the input voltage plus the reference voltage, the latter which may be negative to provide for effective subtractions as well as additions. In order to increase the throughput of the gain stage, two sets of capacitor pairs may be used with one charging from the input voltage while the other is connected to the amplifier to produce an output value.
A rapid and precise “pipelined” analog to digital converter (AC) can be created by connecting a number of these equal capacitor gain stages in series. The first gain stage receives the voltage to be converted and outputs a voltage to the next gain stage for its input, and so forth. Each gain stage doubles the input voltage, then adds a positive voltage reference (+V
ref
), a negative voltage reference (−V
ref
), or zero, as determined by a comparison of the input voltage with two thresholds V
h
and V
1
. Each gain stage also produces two conversion bits dependent on the thresholds process and these are combined to produce the resultant digital conversion value.
The operation and architecture of pipeline AC is also generally described in “A 12-bit 1-Msample/s Capacitor Error-Averaging Pipeline A/D Converter” by Bang-Sup Song, Michael F. Tempest, and Kadabar R. Lakshmikumar in the IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, December 1988, pp. 1324-1333, hereby incorporated by reference. A gain stage suitable for use in such an ADC is described in U.S. Pat. No. 5,574,457 entitled: Switched Capacitor Gain Stage, issued Jun. 12, 1995, assigned to the same assignee as the present invention and hereby incorporated by reference.
Frequently there is a need to simultaneously convert two analog signals into their digital values, for example, in electronic systems having an “in-phase” and “quadrature” signal. Such conversions may be accomplished through the use of two ADCs but at a considerable cost and power penalty.
An alternative approach is to position two sample and hold circuits in front of a single ADC. The sample and hold circuits may simultaneously sample the two input values to be presented in an interleaved sequence to a single analog to digital converter for conversion.
A drawback to this latter approach is that it introduces additional circuitry stage between the input signal and analog converter such as may add noise or systematic errors to the digital value. Further, the buffer amplifiers, timing circuitry for the interleaving, and other circuitry required by the sample and hold circuits significantly increase the cost of the analog to digital converter.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a gain stage adapted to receive two input signals for simultaneous sampling and suitable for use with a pipelined ADC. Significantly, the gain stage of the present invention has significantly fewer parts than would be required with two sample and hold circuits and further, eliminates the introduction of additional circuitry between the input signals and the point of conversion to a digital signal because the gain stage performs both a sample and hold function and a most significant bit extraction.
Generally, the present invention realizes these advantages by using three sets of capacitor pairs. A first and second capacitor pair sample the two input signals while the third is connected across an amplifier. In a next clock cycle, the first capacitor pair is connected across the amplifier and then in a third clock cycle, the first and third capacitor pairs sample the dual inputs while the second capacitor pair is connected across the amplifier. In this way, simultaneous sampling of dual inputs can be obtained with no additional circuitry being introduced in the signal chain between the input signal and the final converted value.
Specifically, the present invention provides a switched capacitor gain stage having a first and second input and an output and including an amplifier having an output connected to the output of the gain stage, and further including a first, second and third capacitor pair. A switch network operates at a first time to switch the first capacitor pair and the second capacitor pair to receive varying voltage from the first and second inputs, respectively, and switch the third capacitor pair across the amplifier and a reference voltage to provide an amplifier output voltage equal to a gain factor times the voltage previously received on the third capacitor pair plus the reference voltage. At a second time after the first time, the switch network switches the first capacitor pair across the amplifier and a reference voltage to provide an amplifier output voltage equal to the gain factor times the voltage previously received on the first capacitor pair plus the reference voltage. At a third time after the second time, the switch network switches the first capacitor pair and the third capacitor pair to receive varying voltages from the first and second inputs, respectively, and switches the second capacitor pair across the amplifier and a reference voltage to provide an amplifier output voltage equal to the gain factor times the voltage previously received on the second capacitor pair plus the reference voltage.
Thus the invention provides a gain stage that may simultaneously sample two input signals for amplification without the introduction of additional circuitry between the input signals and the output of the gain stage. The cycling through of three capacitor pairs allows the same capacitors used for amplification to temporarily store input values for processing.
The invention may provide for simultaneous sampling of two input signals for processing by the gain stage without the duplication of all gain stage elements. By accepting a slightly lower throughput, the present invention provides simultaneous dual input sampling with only a single additional capacitor pair and associated switching circuitry over a dual phase, single channel ADC of the prior art.
The first, second and third capacitor pairs may be matched capacitors on a single integrated circuit.
Thus the invention provides for a dual input gain stage suitable for practical construction on a single integrated circuit. The design's use of standard switched capacitor techniques renders it ideal for integrated circuit implementation.
The present invention may be used in a pipelined dual input ADC in which a plurality of series coupled switched capacitor gain stages are used and the first switched capacitor gain stage has three switched capacitor pairs and alternate simultaneous independent sampling of the dual inputs with the first and second capacitor pairs and the first and third capacitor pairs and sequentially outputs a first output using the first capacitor pair, a second output using the second capacitor pair and a third output using the first capacitor pair and a fourth output using the third capacitor pair.
Thus the invention provides a dual input ADC that requires only modification of the initial gain stage for simultaneous sampling. After the first gain stage, the input values are multiplexed in time to be handled by a slightly modifi

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