Dual injector, floating gate MOS electrically alterable, non-vol

Details Dual injector, floating gate MOS electrically alterable, non-vol Dual injector, floating gate MOS electrically alterable, non-vol

1975-12-29

1977-07-19

James, Andrew J.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

357 41, 357 42, 340173R, H01L 2978, H01L 2702, G11B 1300, G11C 1144

Patent

active

040372421

ABSTRACT:
A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, using process specifications and design rules of the same general character previously developed for single-level metal gate CMOS devices. An electron injector junction (p+
) is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

REFERENCES:
patent: 3740731 (1973-06-01), Ohwada et al.
patent: 3868187 (1975-02-01), Masuoka
patent: 3882469 (1975-05-01), Gosney
patent: 3886583 (1975-05-01), Wang
patent: 3893146 (1975-07-01), Heeren
IBM Technical Disclosure Bulletin; by Terman, vol. 14 No. 12, May 1972 p. 3721.
IBM Technical Disclosure Bulletin; vol. 16 No. 2, July 1973 by James; pp. 690 and 691.
IBM Technical Disclosure Bulletin; by Young, vol. 17 No. 4 Sept. 1974, pp. 1208 and 1209.

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