Dual incrementer

Details Dual incrementer Dual incrementer

1989-07-13

1991-05-21

Shaw, Dale M.

Boots, shoes, and leggings

G06F 750

Patent

active

050180940

ABSTRACT:
An input binary member can be modified by one unit with the assistance of an incrementer, composed of a first circuit CL that generates switch signals (p) from the bit places (d) of the input binary number, these switch signals (p) for the least significant digit (d0) being equal to the value of this digit and, at more significant digits, being generated by AND operation out of the less significant bit of the input binary number. The bit digits of the binary output member (A) are generated with the assistance of an output stage to which the input binary number (D) and the digit signals (P) are supplied. The least significant bit digit of the output binary number is acquired by inversion of the least significant bit place of the input binary number. The more significant bit places of the output binary number are acquired from the allocated binary digits of the input binary number, whereby an arbitrary, an i.sup.th bit digit of the output binary number is equal to the i.sup.th bit digit of the input binary number when the switch signal of the first circuit (CL) that had been acquired through the bit places 0 . . . i=1 is binary 1. Otherwise, this bit digit (d(i)) of the input binary number is connected through to the output in inverted form. The first circuit can be constructed such that respective subcircuits are provided for generating the switch signals, these sub-circuits comprising an identical plurality of stages, to provide a regular structure that can be easily expanded. The output stage must merely provide multiplexers that, dependent on the switch signals, through-connect the bit places of the input plurality either directly or inverted.

REFERENCES:
patent: 4685078 (1987-08-01), Torres
patent: 4709226 (1987-11-01), Christopher
"Parallel-Array Incrementing Network", IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, pp. 6450-6453.
"FET DRAM Look-Ahead Address Incrementer", IBM Technical Disclosure Bulletin, vol. 28, No. 1, Jun. 1985, pp. 71.varies.73.
"MOSFET Look-Ahead Bit Incrementer/Decrementer", IBM Technical Disclosure Bulletin, vol. 28, No. 2, Jul. 1985, pp. 741-742.

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