Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2005-01-04
2005-01-04
Graybill, David E. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S055000, C257S512000, C257S562000, C257S574000, C257S300000, C257S296000, C257S261000, C257S260000, C376S249000, C376S114000
Reexamination Certificate
active
06838713
ABSTRACT:
A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.
REFERENCES:
patent: 4701778 (1987-10-01), Aneha et al.
patent: 4745084 (1988-05-01), Rowson et al.
patent: 4851892 (1989-07-01), Anderson et al.
patent: 5038192 (1991-08-01), Bonneau et al.
patent: 5079614 (1992-01-01), Khatakhotan
patent: 5452245 (1995-09-01), Hickman et al.
patent: 5631478 (1997-05-01), Okumura
patent: 5635737 (1997-06-01), Yin
patent: 5723883 (1998-03-01), Gheewalla
patent: 5727180 (1998-03-01), Davis et al.
patent: 5742099 (1998-04-01), Debnath et al.
patent: 5861641 (1999-01-01), Yoeli et al.
patent: 5917224 (1999-06-01), Zangara
patent: 5923060 (1999-07-01), Gheewala
patent: 5981987 (1999-11-01), Brunolli et al.
patent: 6091090 (2000-07-01), Gheewala
patent: 6177691 (2001-01-01), Iranmanesh et al.
patent: 6242767 (2001-06-01), How et al.
patent: 6307222 (2001-10-01), Brunolli et al.
patent: 6331733 (2001-12-01), Or-Bach et al.
patent: 6445049 (2002-09-01), Iranmanesh
patent: 6445065 (2002-09-01), Gheewala et al.
Chingchi Yao et al., “An Efficient Power Routing Technique to Resolve the Current Crowding Effect in the Power Grid Structure of Gate Arrays”, Seventh Annual IEEE International ASIC Conference and Exhibit.
Abbas El Gamal et al., “BINMOS: A Basic Cell for BiCMOS Sea-of-Gates”, IEEE 1989 Custom Integrated Circuits Conference.
Yoshihiro Okuno et al., “0.8um 1.4MTr. CMOS SOG based on Column Macro-cell”, IEEE 1989 Custom Integrated Circuits Conference.
Breid Duane G.
Colwell Michael J.
Gheewala Tushar R.
Yang Henry H.
Allen Kenneth R.
Graybill David E.
Mitchell James
Townsend and Townsend / and Crew LLP
Virage Logic Corporation
LandOfFree
Dual-height cell with variable width power rail architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual-height cell with variable width power rail architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual-height cell with variable width power rail architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3429713