Dual hardware channels and hardware context switching in a graph

Details Dual hardware channels and hardware context switching in a graph Dual hardware channels and hardware context switching in a graph

1994-03-04

1994-12-06

Evans, Arthur G.

Boots, shoes, and leggings

395163, 395700, 395725, 3642302, 3642412, 3642808, 3642814, 364941, 3649412, 36494392, 3649483, G06F 1520

Patent

active

053718496

ABSTRACT:
An improved graphics processor has rapid response to higher priority tasks. It is implemented with multiple channels of FIFO input circuits and with task interrupt and context switching capability. The graphics processor servicing a first channel task is interrupted when a higher priority task is available in a second channel. Context switching facilitates interrupting of the lower priority first channel task, then saving of the context of the first channel task, then performing higher priority second channel task, then restoring the interrupted first channel task, and then continuing with the processing of the restored first channel task. It is also implemented with concurrent downloading from a host computer and processing by the graphics processor and implemented with general purpose graphics processing capability, including multi-level nested interrupts and nested subroutines.

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