Dual gate structure for a FET and method for fabricating same

Details Dual gate structure for a FET and method for fabricating same Dual gate structure for a FET and method for fabricating same

2006-05-02

2006-05-02

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S504000, C257SE29314

Reexamination Certificate

active

07038260

ABSTRACT:
A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches to adjust the lateral dimension for a first gate. Following the formation of the first gate by implantation or deposition, a buffer region is implanted below the first gate using a complementary dopant and a second sidewall spacer with a thickness that may be the same or greater than the thickness of the first sidewall spacer. Subsequent to the buffer implant, a second gate is implanted beneath the buffer layer using a third sidewall spacer with a greater thickness than the first sidewall spacer.

REFERENCES:
patent: 3381188 (1968-04-01), Zuleeg et al.
patent: 4223328 (1980-09-01), Terasawa et al.
patent: 4404575 (1983-09-01), Nishizawa
patent: 4419586 (1983-12-01), Phipps
patent: 4506282 (1985-03-01), Baliga
patent: 4519024 (1985-05-01), Federico et al.
patent: 4523111 (1985-06-01), Baliga
patent: 4566172 (1986-01-01), Bencuya et al.
patent: 4645957 (1987-02-01), Baliga
patent: 4700461 (1987-10-01), Choi et al.
patent: 4750023 (1988-06-01), Shannon
patent: 4769685 (1988-09-01), MacIver et al.
patent: 4853561 (1989-08-01), Gravrok
patent: 5038266 (1991-08-01), Callen et al.
patent: 5396085 (1995-03-01), Baliga
patent: 5488236 (1996-01-01), Baliga et al.
patent: 5719409 (1998-02-01), Singh et al.
patent: 5808328 (1998-09-01), Nishizawa
patent: 5831288 (1998-11-01), Singh et al.
patent: 5861643 (1999-01-01), Chen et al.
patent: 5945699 (1999-08-01), Young
patent: 6011703 (2000-01-01), Boylan et al.
patent: 6028778 (2000-02-01), Amano
patent: 6064580 (2000-05-01), Watanabe et al.
patent: 6069809 (2000-05-01), Inoshita
patent: 6084792 (2000-07-01), Chen et al.
patent: 6090650 (2000-07-01), Dabrai et al.
patent: 6104172 (2000-08-01), Josephs et al.
patent: 6180519 (2001-01-01), Kuroi et al.
patent: 6236257 (2001-05-01), Si et al.
patent: 6251716 (2001-06-01), Yu
patent: 6307223 (2001-10-01), Yu
patent: 6404157 (2002-06-01), Simon
patent: 6439678 (2002-08-01), Norton
patent: 6551865 (2003-04-01), Kumar et al.
patent: 6696706 (2004-02-01), Pegler
patent: 6777722 (2004-08-01), Yu et al.
patent: 6812079 (2004-11-01), Pegler
patent: 6921932 (2005-07-01), Yu et al.
patent: 2002/0074585 (2002-06-01), Tsang et al.
patent: 2003/0151101 (2003-08-01), Rumennik et al.
patent: 2003/0178646 (2003-09-01), Disney
patent: 2004/0065896 (2004-04-01), Sakamoto
Kang et al.; “A New Type of Transistor: CBT”; IEEE Transactions on Electron Devices; vol. 40; #10; Oct. 93.
“N-Channel Enhancement-Mode MOSFET Transistors”; 2N6660JAN/JANTX/JANTXV; Product Summary; Siliconix; P-37515-Rev. A, Jul. 4, 1994.
General Semiconductor; GF2208; “N-Channel Enhancement-Mode MOSFET”; Jul. 10, 2001.
International Rectifier; IRF1205; HEXFET Power MOSFET; Nov. 3, 1999.
“N-Channel 30V-0.034Ω-22A D2PAK STRIPFET Power MOSFET”; STB22NE03L: Preliminary Data; 6 pgs.; Nov. 2000.
“N-Channel Enhancement-Mode MOSFET Transistors”; 2N66601/VN88AFD; Product Summary; Siliconix; P-37655-Rev. B, Jul. 25, 1994.
Central Semiconductor Corp.; CMPF4391, CMPF4392 CMPF4393, N-Channel JFET; Product Summary.
Fairchild Semiconductor Corporation; “N-Channel/Logic Level Enhancement Mode Field Effect Transistor”; FDP6030L/FDB6030L; Apr. 1998.
Philips Semiconductors; “Powermos Transistor”; BUK463-60A/B; Product Specification; Jul. 1995.
H. Ogiwara, M. Hayakawa, T. Nishimura and M. Nakaoka; “High-Frequency Induction Heating Inverter with Multi-Resonant Mode Using Newly Developed Normally-Off Type Static Induction Transistors”; Department of Electrical Engineering, Ashikaga Institute of Technology, Japan; Department of Electrical Engineering, Oita University, Japan; Department of Electrical Engineering, Kobe University, Japan; pp. 1017-1023.
J. Baliga; “Highvoltage Junction-Gate Field Effect Transistor wth Recessed Gates”; IEEE Transactions on Electron Devices; vol. ED-29; No. 10; Oct. 1982.
J. M. C. Stork et al.; “Small Geometry Depleted Base Bipolar Transistors (BSIT)- VLSI Devices?”; IEEE Transactions on Electron Devices; vol. ED-28; No. 11; Nov. 1981.
Nishizawa et al.;“Analysis of Static Characteristics of a Bipolar Mode SIT (BSIT)”; IEEE Transactions on Electron Devices; vol. ED-29; No. 11; Aug. 1982.
Caruso et al.; “Performance Analysis of a Bipolar Mode FET (BMFET) with Normally Off Characteristics”; IEEE Transactions on Power Electronics; vol. 3; No. 2; Apr. 1988.
Nishizawa et al.; “Fieldeffect Transistor Versus Analog Transistor (Static Induction Transistor)”; IEEE Transactions on Electron Devices; vol. ED-24; No. 4; Apr. 1975.

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