Dual gate MNOS transistor

Details Dual gate MNOS transistor Dual gate MNOS transistor

1976-06-29

1977-11-08

Wojciechowicz, Edward J.

357 51, 357 54, 357 59, H01L 2978, H01L 2702, H01L 2934, H01L 2904

Patent

active

040578208

ABSTRACT:
A dual gate MNOS memory transistor is disclosed. The transistor includes drain and source regions of a first conductivity type formed in a substrate of a second conductivity type. The region of the substrate between the drain and source regions forms the channel of the transistor. First and second insulating layers forming a charged trapping structure overlie the channel region. A first gate having a width less than the width of the channel overlies the central portion of the channel region. A second gate, insulated from the first gate, overlies the first gate and the remainder of the channel region. The threshold voltage of the transistor is shifted by selectively biasing the gates and the substrate. High and low threshold voltage states are used to represent the two values of a digital signal.

REFERENCES:
patent: 3436623 (1969-04-01), Beer
patent: 3633078 (1972-01-01), Dill et al.

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