Dual gate FET and process

Details Dual gate FET and process Dual gate FET and process

2001-01-09

2003-01-07

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

C257S365000

Reexamination Certificate

active

06504173

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the fabrication of metal oxide semiconductor field effect transistor (MOSFET) devices, and in particular to a method of fabricating dual gate MOSFET devices wherein the top and bottom gates of the MOSFET devices are mirror images of each other. The present invention is also directed to MOSFET devices, and in particular to dual gate FET devices which comprise a top gate and a bottom gate that are substantially identical to each other, in terms of size, conductivity and uniformity of dopant throughout the two gate regions.
BACKGROUND OF THE INVENTION
It is well known that a dual gate or double gate MOSFET device has several advantages over conventional single gate MOSFET devices. Specifically, the advantages for dual gate MOSFET devices over their single gate counterparts include: a higher transconductance, lower parasitic capacitance, and improved short-channel effects. For instance, Monte-Carlo simulation has been previously carried out on a 30 nm channel dual agate MOSFET device and has shown that the dual gate device has a very high transconductance (2300 mS/mm) and fast switching speeds (1.1 ps for nMOSFET). Moreover, improved short-channel characteristics are obtained down to 20 nm channel length with no doping needed in the channel region. This circumvents all the tunneling breakdown, dopant quantization, and dopant depletion problems associated with channel doping that are normally present with single gate MOSFET devices.
Despite these advantages, however, there is no satisfactory way of fabricating a dual gate structure wherein the bottom and top gates are mirror images of each other, i.e. they are substantially identical to each other in terms of conductivity, size and uniformity of dopant throughout the two gate regions. Previous efforts on fabricating dual gate MOSFETs generally fall into one of the following three categories:
(a) Etch silicon into a pillar structure and deposit gates around it.
(b) Make a conventional single-gate MOSFET, then use either selective epitaxy or bond-and-etch-back techniques to form the second gate.
(c) Start with a thin silicon-on-insulator (SOI) film, pattern a strip and dig a tunnel across it by etching the buried oxide. Then, deposit gate electrodes in the tunnel and on top of the SOI film.
There are serious drawbacks in all of the foregoing prior art approaches. For example, in (a), it is difficult to form a vertical pillar as thin as 10 nm with good thickness control and free of reactive ion etching (RIE) damage. In (b), it is difficult to keep the top and bottom oxides at the same thickness and to have the gates self-aligned to each other, and in (c), thickness control and top/bottom gate self-alignment are major problems.
Moreover, current prior art proposals to form the bottom gate of a dual gate MOSFET device are mostly done by ion implantation through a SOI structure. Several drawbacks using this approach also exist. These drawbacks include: ion implantation causes defects in device areas; the gate oxide quality of the bottom gate is poor; and the bottom gate is not isolated from the structure. Other known methods to form dual gate structures such as surround gate structures and 3-D devices are either too complicated or would consume too much of the surface area of the device. Thus, those methods are presently unsuitable for current dual gate FET device manufacturing.
In view of the drawbacks mentioned hereinabove with prior art methods for fabricating dual gate MOSFET devices, it would be beneficial if a new process was developed that is relatively simple, yet effective in fabricating dual gate devices which avoids the aforementioned shortcomings of the prior art.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a dual gate structure which contains a bottom gate and a top gate that are mirror images of each other (i.e. substantially identical, in terms of conductivity, size and uniformity of dopant throughout the two gate regions).
Another object of the present invention is to provide a method of Fabricating a dual gate structure wherein the method provides the following advantages which are heretofore unobtainable utilizing prior art processes: the bottom gate has improved quality; the bottom gate is completely isolated from the substrate; no high energy ion implant is required; the top and bottom gates can be aligned easily and result in low overlap capacitance; and the device size is the same as that of a conventional single gate FET device.
These and other objects and advantages are achieved in the present invention by utilizing a novel shallow trench isolation process which is used in the present invention for polishing and alignment purposes. Specifically, the method of the present invention, which forms a dual gate structure wherein the top gate and bottom gate are mirror images of each other, comprises the steps of:
(a) providing a structure comprising a first oxide layer formed over a silicon substrate, wherein said first oxide layer contains a first gate region embedded therein and said silicon substrate contains two regions each of which comprises a bottom nitride layer and a top oxide layer formed between said first gate region;
(b) bonding an exposed surface of said first oxide layer to a handling wafer;
(c) polishing away a portion of said silicon substrate stopping at said bottom nitride layer;
(d) removing said nitride layer from said polished silicon substrate;
(e) growing an oxide region in and on said polished silicon substrate provided in step (d);
(f) forming a protective layer over said structure provided in step (e);
(g) opening a hole in the structure extending down to said first gate region;
(h) depositing a layer of polysilicon over the structure provided in step (g) including in said hole;
(i) patterning the polysilicon layer and developing the pattern so as to provide a second gate region directly over the underlying first gate region;
(j) implanting source and drain regions in said silicon substrate adjacent to said first and second gate regions; and
(k) annealing the structure provided in step (j).
It is noted that the terminology “first gate region” refers to the bottom gate region of the MOSFET device and “second gate region” refers to the top gate region of the MOSFET device.
Another aspect of the present invention relates to a dual gate structure which comprises a top gate electrode and a bottom gate electrode, wherein said top gate electrode is a mirror image of the bottom gate electrode and they are substantially identical to each other in terms of conductivity, size and uniformity of dopant concentration.


REFERENCES:
patent: 4784970 (1988-11-01), Solomon
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5034343 (1991-07-01), Rouse et al.
patent: 5120666 (1992-06-01), Gotou
patent: 5188973 (1993-02-01), Omura et al.
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5296727 (1994-03-01), Kawai et al.
patent: 5376559 (1994-12-01), Mukai et al.
patent: 5420048 (1995-05-01), Kondo
patent: 5436173 (1995-07-01), Houston
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5580802 (1996-12-01), Mayer et al.
patent: 5583362 (1996-12-01), Maegawa
patent: 5646058 (1997-07-01), Taur et al.
patent: 5702963 (1997-12-01), Vu et al.
patent: 5801397 (1998-09-01), Cunningham
patent: 6004837 (1999-12-01), Gambino et al.

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