Dual-gate device and method

Details Dual-gate device and method Dual-gate device and method

2007-02-06

2009-02-24

Nhu, David (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S701000, C257S347000, C257SE21170, C257SE21006, C257SE21278, C257SE21304, C257SE21646

Reexamination Certificate

active

07495337

ABSTRACT:
A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.

REFERENCES:
patent: 5616934 (1997-04-01), Dennison et al.
patent: 5633196 (1997-05-01), Zamanian
patent: 5894160 (1999-04-01), Chan et al.
patent: 6054734 (2000-04-01), Aozasa et al.
patent: 6140688 (2000-10-01), Gardner et al.

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