Dual gate CMOS transistor circuits having reduced electrode capa

Details Dual gate CMOS transistor circuits having reduced electrode capa Dual gate CMOS transistor circuits having reduced electrode capa

1982-05-03

1984-08-28

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307450, 357 23, H03K 19017, H03K 19094, H03K 1920

Patent

active

044685742

ABSTRACT:
Dual gate P-channel and N-channel transistors are interconnected in various configurations to provide logic circuits such as inverters, NAND gates, NOR gates, and Exclusive-OR gates.

REFERENCES:
patent: 3657614 (1972-04-01), Cricchi
patent: 4041519 (1977-08-01), Melen
patent: 4074150 (1978-02-01), Buckley et al.
patent: 4122360 (1978-10-01), Kawagai et al.
patent: 4306352 (1981-12-01), Schrader
patent: 4319263 (1982-03-01), Rao
patent: 4417161 (1983-11-01), Uya
W. P. Noble, Jr., "Short-Channel Effects in Dual-Gate Field-Effect Transistors", in IEEE Int. Electron Dev. Mtg., Dig. Tech. Papers, Dec. 1978, pp. 483-486.
Hans G. Dill, "A New Insulated Gate Tetrode With High Drain Breakdown Potential and Low Miller Feedback Capacitance," IEEE Transactions on Electron Devices, vol. ED-15, No. 10, Oct. 1968.

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