Dual-gain loop circuitry for programmable logic device

Details Dual-gain loop circuitry for programmable logic device Dual-gain loop circuitry for programmable logic device

2006-03-28

2006-03-28

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C331S00100A

Reexamination Certificate

active

07019570

ABSTRACT:
A loop circuit (PLL or DLL) uses a dual-gain voltage-controlled component (VCO or VCDL) to achieve a phase (and frequency) lock with reduced jitter. A coarse control feedback path includes a detector for achieving an approximate lock. This path operates over a wide range and therefore feeds a VCO or VCDL input with relatively high gain. However, input on that path is fixed once coarse frequency lock is achieved, so it does not contribute to jitter. A fine control path includes a detector whose output fine tunes the lock. Although this path is susceptible to noise, its operating range is relatively small, so its VCO or VCDL input has relatively low gain. Therefore jitter from magnification of noise by that gain is relatively small. The loop circuit can be used in a programmable logic device, in which case various loop parameters may be determined by programmable values.

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