Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Patent
1998-03-31
2000-03-21
Pan, Daniel H.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
712211, 712226, 712229, G06F 915
Patent
active
060414049
ABSTRACT:
An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.
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Abdallah Mohammad
Chennupaty Srinivas
Coke Jim
Cranford Mike
Kong Katherine
Intel Corporation
Nguyen Dzung
Pan Daniel H.
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