Dual function error correcting system

Details Dual function error correcting system Dual function error correcting system

1980-11-14

1982-11-16

Atkinson, Charles E.

Excavating

371 38, G06F 1110

Patent

active

043597726

ABSTRACT:
A dual function cyclic code error correcting method and system are disclosed for correcting from a single syndrome byte a random single-bit error which occurs in a multi-byte data word or, alternatively, correcting a multi-bit error in one byte of the data word by providing an indication of the location of the byte in error, and employing the same syndrome byte to determine the error pattern of the multi-bit error so the multi-bit error can be corrected.
The method involves non-zero syndrome processing steps which comprise a first series of steps which function to determine if the non-zero syndrome correlates to a 1-bit error in one of the byte positions of the data word being protected, and if so, to automatically correct the single-bit error by processing the entire byte containing the single-bit error. If no correlation of the syndrome byte is established with a single-bit error, then the byte position in the data word of the multi-bit error is used during a second series of steps to process the same non-zero syndrome byte to determine the pattern of the multi-bit error in the defective byte so that the pattern can be employed to correct the defective byte.
The method and apparatus disclosed also identify the location of repetitive multi-byte errors by generating a byte parity vector for each data word and using these byte parity vectors to identify the location in each data word of repetitive errors of the multi-bit type.
The method and system are advantageously employed in an environment in which the probability of a random 1-bit error occurring during the processing of data is, for example, one in 10.sup.8 processed data bits, but where the probability of repetitive multi-bit errors occurring in successively processed data words is relatively high after a multi-bit error occurs in one byte.

REFERENCES:
patent: 3487362 (1969-12-01), Frey, Jr.
patent: 3638182 (1972-01-01), Burton et al.
patent: 3742449 (1973-06-01), Blair
patent: 3755779 (1973-08-01), Price
patent: 3859630 (1975-01-01), Bennett
A. M. Patel, Dual-Function ECC Employing Two Check Bytes per Word, IBM Technical Disclosure Bulletin, vol. 24, No. 2, Jul. 1981, pp. 1002-1004.

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