Dual function ECC system with block check byte

Details Dual function ECC system with block check byte Dual function ECC system with block check byte

1980-11-14

1982-11-09

Atkinson, Charles E.

Excavating

371 38, G06F 1110

Patent

active

043588484

ABSTRACT:
An improved ECC method and system are disclosed for correcting either a random single-bit error, or alternately, a multi-bit error in one byte of a data word from a single syndrome byte. The improvement involves determining the location of the multi-bit error in successive data words which result because of a failure in one of a plurality of failure independent storage units employed for storing a block of multi-byte words.
The location of the defective byte position is determined by summing each non-zero syndrome byte that is developed for each multi-byte word that is processed to produce a summed syndrome byte .SIGMA.S.noteq.0. This summed syndrome byte is then employed to generate a set of vectors which are positionally related in an m-sequence to the summed syndrome byte. A block syndrome byte, developed during the processing of a number of words and representing the sum modulo-2 of the error pattern in each word of the block, is compared to each of the set of vectors. The position of the vector relative to the summed syndrome byte compared to the block syndrome byte then provides an indication of the byte position in each word which is in error. With the defective byte position identified, the individual syndrome bytes for each word are then employed to develop for each word the correct error pattern for the defective byte position of each word.

REFERENCES:
patent: 3487362 (1969-12-01), Frey, Jr.
patent: 3638182 (1972-01-01), Burton et al.
patent: 3742449 (1973-06-01), Blair
patent: 3755779 (1973-08-01), Price
patent: 3859630 (1975-01-01), Bennett
A. M. Patel, Dual-Function ECC Employing Two Check Bytes per Word, IBM Tech, Discl. Bulletin, vol. 24, No. 2, Jul. 1981, pp. 1002-1004.

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