Communications: electrical – Systems – Selsyn type
Reexamination Certificate
1999-07-14
2001-12-18
Tong, Nina (Department: 2632)
Communications: electrical
Systems
Selsyn type
C340S315000, C333S017300, C333S032000, C333S124000, C343S822000, C326S030000
Reexamination Certificate
active
06331815
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dual-frequency matching circuit that enables impedance matching at two separate frequencies simultaneously, and more particularly to an improvement of the matching circuit that can be suitably used in the microwave band.
2. Description of the Related Art
FIG. 9
is a schematic diagram showing a conventional dual-frequency matching circuit cascaded with a field-effect transistor (hereinafter referred to just as an “FET”, or an “FET transistor”), as disclosed in the “Dual-frequency matching technique and its application to an octave-band (30-60 GHz) MMIC amplifier” by NAKAJIMA, M, MURAGUCHI, in IEICE TRANS, ELECTRON., VOL.E80-C, No. 12, December 1997.
In the figure, reference numeral
1
denotes an input terminal of the matching circuit, numeral
2
denotes an output terminal of the matching circuit, numeral
47
denotes a transmission line provided between the input terminal
1
and the output terminal
2
, numeral
48
denotes a shorted stub provided between the input terminal
1
and the transmission line
47
, the length of which is a quarter-wavelength &lgr;/4 at a high angular frequency &ohgr;
H
, numeral
49
denotes an open stub provided between the input terminal
1
and the transmission line
47
, and reference numeral
50
denotes an FET transistor, the gate of which is connected to the output terminal
2
.
FIG. 10
denotes a Smith Chart for explaining the matching method in the conventional dual-frequency matching circuit. In the figure, reference numeral
51
denotes a load impedance generated in a case that a low-frequency signal f
L
is applied to the FET transistor
50
, reference numeral
52
denotes an impedance generated in a case that a high-frequency signal f
H
is applied to the FET transistor
50
, and reference numeral
53
denotes a constant conductance circle (a constant conductance circle of 0.02 S, for example).
First, by setting the length of the transmission line
47
to a predetermined length, the two impedances of the above-mentioned FET transistor are set on to the constant conductance circle
53
. Reference numeral
54
denotes a thus obtained transformed impedance of the case that the low-frequency signal f
L
is applied, whereas the reference numeral
55
denotes a transformed impedance of the case that the high-frequency signal f
H
is applied.
Thereafter, by setting the length of the open stub
49
to a predetermined length, the above-mentioned two impedances are shifted along the constant conductance circle
53
so as to be matched with each other, and reference numeral
56
denotes a point at which they are matched. In this way, the conventional matching circuit enables an impedance matching at two separate frequencies f
L
and f
H
.
The operation of the above conventional dual-frequency matching circuit is as follows.
When a signal is to be input through the input terminal
1
to the EET transistor
50
, no reflected wave due to the input signal is generated at the above two matching frequencies f
L
and f
H
.
Since the conventional dual-frequency matching circuit is configured as such, two input impedances of the FET transistor
50
at two different frequencies are transformed on to the constant conductance circle
53
only on the basis of the length of the transmission line
47
, so that if the length of the transmission line
47
is determined in such a manner that an impedance at one of the two frequencies is shifted on to the constant conductance circle
53
, the other frequency at which the impedance can be shifted on to the constant conductance circle
53
is automatically determined, so that there has been a problem that the matching of impedances at two arbitrarily selected frequencies is not made possible.
Further, as a transmission line
47
is adopted in the conventional dual-frequency matching circuit, if the matching is to be performed in a low-frequency band, a considerably long transmission line is required, so that the size of the frequency-matching circuit as a whole is also made too large.
SUMMARY OF THE INVENTION
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide a matching circuit capable of performing an impedance matching at two arbitrary frequencies.
In order to achieve the above object, the dual-frequency matching circuit according to the first aspect of the present invention is constructed such that it comprises an output terminal to which a load is connected, an input terminal through which an input signal is input to the load, a series resonance circuit, which is composed of a series capacitor and a series inductor connected in series to the series capacitor, and disposed in such a manner as to be connected in series to the load when observed from the input terminal side, and a parallel resonance circuit, which is composed of a parallel capacitor and a parallel inductor connected in parallel to the parallel capacitor, and disposed in such a manner as to be connected in parallel to the entire portion of the series resonance circuit and the load when observed from the input terminal side.
In the dual-frequency matching circuit constructed as above, on condition that the load connected to the output terminal is formed by a load resistor and a load capacitor mutually connected in series, and that the resistance of the load resistance is R
i
, the capacitance of the load capacitor is C
gs
, two matching angular frequencies are &ohgr;
L
and &ohgr;
H
, respectively, and matching admittance is Y
0
, the inductance L
1
of the series inductor, the capacitance C
1
of the series capacitor, the inductance L
2
of the parallel inductor and the capacitance C
2
of the parallel capacitor are set in such a manner as to satisfy the following Formulae 1:
L
1
=X
g
/(&ohgr;
H
−&ohgr;
L
)
C
1
=(&ohgr;
H
−&ohgr;
L
)*C
gs
/(C
gs
*&ohgr;
H
*&ohgr;
L
*X
g
−(&ohgr;
H
−&ohgr;
L
))
L
2
=(&ohgr;
H
−&ohgr;
L
)*R
i
/(&ohgr;
H
*&ohgr;
L
*Y
o
*X
g
)
C
2
=Y
o
*X
g
/((&ohgr;
H
−&ohgr;
L
)*R
i
)
X
g
=(R
i
/Y
0
−R
i
*R
i
)
½
(Formulae 1)
The dual-frequency matching circuit according to the second aspect of the present invention is constructed such that it comprises an output terminal to which a load is connected, an input terminal through which an input signal is input to the load, a parallel resonance circuit, which is composed of a parallel capacitor and a parallel inductor connected in parallel to the parallel capacitor, and disposed in such a manner as to be connected in series to the load when observed from the input terminal side, and a series resonance circuit, which is composed of a series capacitor and a series inductor connected in series to the series capacitor, and disposed as being connected in parallel to the load when observed from the input terminal side.
In the dual-frequency matching circuit constructed as above, the load connected to the output terminal is formed by a load resistor and a load capacitor mutually connected in series, wherein on condition that the resistance of the load resistance is R
i
, the resistance of the load capacitor is C
gs
, two matching angular frequencies are &ohgr;
L
and &ohgr;
H
, respectively, and matching impedance is Z
0
, the inductance L
1
of the series inductor, the capacitance C
1
of the series capacitor, the inductance L
2
of the parallel inductor, and the capacitance C
2
of the parallel capacitor are set in such a manner as to satisfy the following Formulae 2:
L
1
=(&ohgr;
H
*(&bgr;
L
−B
gL
)−&ohgr;
L
*(&bgr;
H
+B
gH
))/((&ohgr;
H
*&ohgr;
H
−&ohgr;
L
*&ohgr;
L
)(&bgr;
L
−B
gL
)(&bgr;
H
+B
gH
))
C
1
=(&ohgr;
H
*&ohgr;
H
−&ohgr;
L
*&ohgr;
L
)(&bgr;
L
−B
gL
)(&bgr;
H
+B
gH
)/(&ohgr;
H
*&ohgr;
L
*(&ohgr;
L
*(&bgr;
L
−B
gL
)−&ohgr;
H
*(&bgr;
H
+B
gH
)))
L
2
=Z
o
*(&ohgr;
H
*&ohgr;
H
−&ohgr;
L
*&ohgr;
L
)*B
gH
*B
gL
/(&ohgr;
H
*&ohgr
Itoh Yasushi
Oshima Takeshi
Uchida Hiromitsu
Mitsubishi Denki & Kabushiki Kaisha
Rothwell Figg Ernst & Manbeck
Tong Nina
LandOfFree
Dual-frequency matching circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual-frequency matching circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual-frequency matching circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2558492