Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1998-04-08
2001-06-05
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185100, C257S316000
Reexamination Certificate
active
06243289
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a unique cell structure for a non-volatile memory used in erasable programmable, read only memory devices such as EEPROM and flash memory. More particularly the invention relates to a cell structure having a transistor which employs a pair of floating gates to store multi-bit binary data and to methods for fabricating and operating the memory cell.
2. Discussion of the Related Art
Nonvolatile memory cells are known in which multiple bits of data can be stored by placing various levels of charge on the floating gate of the cell transistor which in turn affects the transistor threshold voltage Vt. By storing differing levels of charge and thus obtaining different levels of threshold voltage Vt a cell can store more than one bit of information therein. For example, in order to store two binary bits four levels of charge and correspondingly levels of Vt may be used. During a read operation, a decoder senses the transistor threshold Vt to determine the corresponding binary value of the multi-bit information, e.g. 00, 01, 10, 11.
In order to store higher densities of binary bits in the cell, it is necessary to correspondingly increase the number of Vt voltage levels corresponding to the number of bits of information which are stored. For example, in order to store three bits, eight levels of charge must be stored. As higher voltages are used, for charge storage, it introduces problems in the memory array including requiring a higher operating voltage, more power dissipation, and complex circuitry for reading, erasing and decoding the binary information. Moreover, if the number of charge levels increases without increasing the supply voltage, it becomes more difficult to detect the correct stored charge level. Accordingly, it becomes progressively more difficult to store larger numbers of digits of information in an erasable programmable memory cell having a floating gate.
SUMMARY OF THE INVENTION
The present invention is designed to alleviate some of the problems associated with the storage of multi-bit binary information in the memory cell of an erasable programmable read only memory array. The present invention provides two separate floating gates for each transistor within the memory cell. The control gate of the transistor is connected to a word line provided over both floating gates while each of the source and drain regions of the transistor are connected to respective digit lines. By appropriately controlling the voltage differential applied to the word line and digit lines and timing of application of the voltage differential, separate charges can be stored and read from each of the two floating gates of the transistor. By utilizing two separate floating gates to respectively store charges within the transistor, the reading, writing, erasing and decoding of the multi-bit information can be done with lower voltages and power dissipation than would otherwise be required for a single floating gate transistor and the decoding of many levels of stored charges is not required. Therefore, repeated storage of multi-bit data does not degrade the cell as much as occurs with a single floating gate transistor cell.
Thus, the memory cell of the invention can be used to store two or more bits of information by separately controlling the charges stored in each of the floating gates.
The invention also relates to fabrication methods for the dual floating gate transistor as well as to a method for operating the transistor to write and read multi-bit digital data to and from the memory cell.
It should be understood that the memory cell of the invention can be used in EEPROM flash memory arrays, and other erasable programmable read only memory arrays. For purposes of simplified discussion, this specification will discuss the invention in the context of a flash memory array; however, it should be understood that the memory cell of the invention can be used in any read only memory array which is electronically erasable and reprogrammable.
The foregoing and other advantages and features of the invention will be more readily appreciated from the following detailed description of the invention which is provided in connection with the accompanying drawings.
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Benistant Francis L.
Gonzalez Fernando
Dickstein , Shapiro, Morin & Oshinsky, LLP
Mai Son
Micro)n Technology, Inc.
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