Dual floating gate EEPROM cell array with steering gates shared

Details Dual floating gate EEPROM cell array with steering gates shared Dual floating gate EEPROM cell array with steering gates shared

1999-06-30

2000-11-21

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518501, 257315, G11C 1604

Patent

active

061512486

ABSTRACT:
An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.

REFERENCES:
patent: 4336603 (1982-06-01), Kotecha et al.
patent: 4380057 (1983-04-01), Kotecha et al.
patent: 4417264 (1983-11-01), Angle
patent: 4855955 (1989-08-01), Cioaca
patent: 5021999 (1991-06-01), Kohda et al.
patent: 5043940 (1991-08-01), Harari
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5095461 (1992-03-01), Miyakawa et al.
patent: 5159570 (1992-10-01), Mitchell et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5210047 (1993-05-01), Woo et al.
patent: 5278439 (1994-01-01), Ma et al.
patent: 5297148 (1994-03-01), Harari et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5364806 (1994-11-01), Ma et al.
patent: 5411905 (1995-05-01), Acovic et al.
patent: 5412600 (1995-05-01), Nakajima
patent: 5414693 (1995-05-01), Ma et al.
patent: 5486714 (1996-01-01), Hong
patent: 5576567 (1996-11-01), Mori
patent: 5606521 (1997-02-01), Kuo et al.
patent: 5616510 (1997-04-01), Wong
patent: 5636160 (1997-06-01), Omino et al.
patent: 5643814 (1997-07-01), Chung
patent: 5661053 (1997-08-01), Yuan
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5714412 (1998-02-01), Liang et al.
patent: 5786612 (1998-07-01), Otani et al.
patent: 5812449 (1998-09-01), Song
patent: 5991201 (1999-11-01), Chang
patent: B15172338 (1997-07-01), Mehrotra et al.
Alberts et al., "Multi-Bit Storage FET EAROM Cell", IBM Technical Disclosure Bulletin, vol. 24, No. 7A, Dec. 1981, pp. 3311-3314.
Kamiya et al., "EPROM Cell with igh Gate Injection Efficiency", Int'l Electron Device Mtg., Technical Digest, Dec. 13, 1982, pp. 741-744.
Ma et al., "A Dual-bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories", 1994 IEEE pp. 3.5.1 thru 3.5.4.
Pein et al, "Performance of the #-D Sidewall Flash EPROM Cell", International Electron Devices Meeting Technical Digest, Washington DC, Dec. 5-8, 1993, pp. 2.1.1 thru 2.1.4.
Kuo et al., "TEFET--A High Density, Low Erase Voltage, Trench Flash EEPROM", 1994 Symposium on VLSI Technology, Honolulu, Jun. 7-9, 1994, pp. 51-52.

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