Dual flip-flop detector type phase locked loop incorporating sta

Details Dual flip-flop detector type phase locked loop incorporating sta Dual flip-flop detector type phase locked loop incorporating sta

1996-03-29

1997-08-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 331 25, 331 27, H03L 7093

Patent

active

056592680

ABSTRACT:
Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop. The phase offset is due to circuit delays in the phase detector which result in the issuance of simultaneous "pump up" and "pump down" signals, present even during apparent phase lock. A second pair of flip-flops (or a single flip-flop) of the same type used in the phase detector is sampled to obtain a compensating signal which is applied to the reference input of a differential amplifier in the loop filter. Each of the second pair of flip-flops is forced to assume a permanent state (for example, set) such that their respective Q and Q-bar outputs are always representative of the logic voltage levels at the corresponding outputs of the flip-flops in the phase detector from which the "pump up" and "pump down" are sourced. These voltages are summed to obtain a voltage exactly at the midpoint between logic "1" and logic "0", and this summed voltage is employed as the reference signal to the differential amplifier, thereby exactly counteracting any offset component of the voltage appearing at the signal input to the amplifier which is developed during normal operation of the phase detector, filter and summing circuit of the phase locked loop at apparent phase lock.

REFERENCES:
patent: 4599570 (1986-07-01), Cloke

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