Dual-FET sample and hold circuit

Details Dual-FET sample and hold circuit Dual-FET sample and hold circuit

1979-11-15

1981-12-29

Mullins, James B.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307572, H03K 5153

Patent

active

043084680

ABSTRACT:
An improved sample and hold circuit is disclosed. One field effect transistor (FET) is used as a switch between a variable input voltage connected to the source and a holding capacitor connected to the drain on the output line. The sampling pulse is applied to the gate, and is unavoidably coupled through the gate-to-drain capacitance to become a noise pulse on the output line. To cancel this pulse, a second compensating FET is provided. The sources and drains of these FETs are connected and the gate of the second FET receives a sampling pulse of opposite polarity. The second FET is biased off but the gate pulse is coupled through the source and drain capacitance to the first FET where it is used to cancel the original noise pulse on the output line.

REFERENCES:
patent: 3586880 (1971-06-01), Fitzwater
patent: 3719832 (1973-03-01), Waaben
patent: 4048525 (1977-09-01), Goldberg et al.
"Improved Sample & Hold", Electronic (G.B.), No. 50, Apr. 25, 1974, p. 53.
"Analog Switches and Their Applications", Siliconix Incorporated, 1976, pp. 4-18 to 4-19.

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