Dual FET circuits having floating voltage bias

Details Dual FET circuits having floating voltage bias Dual FET circuits having floating voltage bias

1990-11-30

1993-03-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307571, 307574, 307284, 307584, H03K 1716, H03K 335

Patent

active

051912384

ABSTRACT:
Prior art single FET switches suffer the disadvantage of uncertainties in the turning on and off thereof due to the high back bias voltage required. In the present system, by using a dual FET configuration, with the respective source regions of the FETs connected at a common node and a floating bias voltage source connecting the common node to the respective gate regions of the dual FET, a switching circuit which is capable of handling higher voltages and whose dB compression stays constant is provided. Since the dual FET circuit is symmetrical, depending on the polarity of the biasing voltage, the drain and the source regions are interchangeable.

REFERENCES:
patent: 4588243 (1985-12-01), Schutten et al.
patent: 4705967 (1987-11-01), Vasile
Elektronik "270W Switching Network With SIPMOS Transistors", No. 11, 4 Jun. 1982.

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