Dual fault-masking redundancy logic circuits

Details Dual fault-masking redundancy logic circuits Dual fault-masking redundancy logic circuits

1985-10-28

1988-01-12

Smith, Jerry

Excavating

307219, 307441, 307445, 371 36, G06F 1118

Patent

active

047196297

ABSTRACT:
An error correcting logic circuit for masking faults on dual redundant interconnections. Both interconnections are inmput to a NAND or AND circuit which includes pull-up resistors to a high potential. The outputs of all the NAND circuits are connected to dual redundant logic circuits, each of which has an emitter-follower output with a load resistor to ground. The outputs of the redundant logic circuits provide the redundant interconnections to other similar error correcting logic circuits.

REFERENCES:
patent: 3305735 (1967-02-01), Moreines
patent: 3524073 (1970-08-01), Tobin
patent: 3558905 (1971-01-01), Oshima
patent: 3800164 (1974-03-01), Miller
patent: 3859513 (1975-01-01), Chuang
patent: 4342112 (1982-07-01), Stodola
patent: 4617475 (1986-10-01), Reinschmidt

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