Dual EPROM cells on trench walls with virtual ground buried bit

Details Dual EPROM cells on trench walls with virtual ground buried bit Dual EPROM cells on trench walls with virtual ground buried bit

1990-01-19

1991-05-21

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 55, 365185, H01L 27115

Patent

active

050179772

ABSTRACT:
One embodiment of the present invention provides an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches formed in a semiconducting substrate. Simultaneous with the fabrication of these trench wall transistors, column lines are formed between the trenches to the top surface in the bottom of the trenches which extend from one end to the other of the memory array.

REFERENCES:
patent: 4163988 (1979-08-01), Yeh et al.
patent: 4169291 (1979-09-01), Roessler
patent: 4222062 (1980-09-01), Trotter et al.
patent: 4353082 (1982-10-01), Chatterjee
patent: 4364074 (1982-12-01), Garnache et al.
patent: 4542396 (1985-09-01), Schutten et al.

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