Dual ended folded bit line arrangement and addressing scheme

Details Dual ended folded bit line arrangement and addressing scheme Dual ended folded bit line arrangement and addressing scheme

1987-08-06

1989-01-24

Hecker, Stuart N.

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

365230, 36523003, 365210, 365 51, G11C 506, G11C 700, G11C 800

Patent

active

048005258

ABSTRACT:
A scheme for addressing memory cells in random access memory arrays includes bit lines divided into a plurality of segments. Each pair of bit lines has a sense amp at each end coupled to both bit lines in the pair. Word lines address memory cells coupled to each bit line of the pair. When a pair of memory cells is accessed, the bit lines are electrically divided so that one memory cell is coupled to one sense amp through one bit line, and the other memory cell is coupled to the other sense amp through the other bit line. The memory cells can be coupled to the bit lines through segment lines, with each segment line connecting a subset of the memory cells to a bit line, in order to reduce capacitances presented to the sense amps. An alternating linear array of sense amps and bit line pairs can be used to increase overall density of the memory array by allowing sense amps to access more than one bit line pair. The bit lines are addressed so that each sense amp receives data from one one bit line pair at a time. Segment lines having no currently addressed memory cells can be coupled to the sense amps in order to better balance input capacitances presented thereto. Selecting the bit line sections, segments, and memory cells in the proper order minimizes the effect of noise due to stray capacitances by causing them to appear as a common mode signal across the bit line pairs.

REFERENCES:
patent: 4367540 (1983-01-01), Shimohigashi
patent: 4581720 (1986-04-01), Takemae et al.
patent: 4590588 (1986-05-01), Itoh et al.

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