Dual-edge synchronized data sampler

Details Dual-edge synchronized data sampler Dual-edge synchronized data sampler

2007-03-13

2007-03-13

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S091000

Reexamination Certificate

active

11015322

ABSTRACT:
A dual-edge synchronized sampler having an efficient implementation for high speed and high performance operation is described. The sampler receives a data input signal and a clock input signal and uses an asynchronous level mode state machine to sample the data input signal responsive to level changes in the clock input signal. In some embodiments, the sampler includes at least one differential logic block for implementing the asynchronous level mode state machine. The sampler has symmetric clock-to-Q propagation delays for both rising and falling edges of the clock input signal. The sampler may include toggle functionality, and may include edge control logic for configuring the sampler as one of a rising edge and falling edge sampler.

REFERENCES:
patent: 2002/0168043 (2002-11-01), Sander
U.S. Appl. No. 11/015,674, filed Dec. 17, 2004, Kaviani.
U.S. Appl. No. 10/837,186, filed Apr. 30, 2004, Morrison et al.
U.S. Appl. No. 10/954,889, filed Sep. 29, 2004, Kaviani et al.
Xilinx, Inc.; “Virtex-II Platform FPGA Handbook”; published Dec. 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 161-183.

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