Electrical pulse counters – pulse dividers – or shift registers: c – Particular output circuits for counter
Reexamination Certificate
2000-09-14
2002-09-10
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Particular output circuits for counter
C377S051000, C377S107000
Reexamination Certificate
active
06449329
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital electronic circuits and systems. More specifically, the present invention relates to counters.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Counters are used in a variety of digital circuits to track events. In addition, counters are used to synthesize clock signals and other waveforms. Generally, a second (lower) clock frequency is synthesized from a first (higher) clock frequency using a counter. Typically, a simple M/N:D type counter is used, where M and N are integers, D is the duty cycle threshold, M is the desired frequency of the synthesized clock signal and N is the frequency of the source or reference clock.
The counter is typically a rising edge counter that counts pulses from the first clock frequency and periodically outputs a pulse at the second clock frequency. That is, the M/N counter outputs M pulses after counting N rising edges pulses of a reference clock.
This is relatively straightforward when the first clock frequency is an integer multiple of the second clock frequency. However, when the first clock is not an integer multiple of the second clock, the task of clock synthesis becomes a bit more challenging. For example, if the reference clock is a 5 megahertz (MHz) clock, and it is necessary to synthesize a 1.5 MHz clock, in accordance with conventional teachings, the M/N counter, programmed to M=3 and N=10, effectively multiplies the reference clock by a 3/10 or outputs three clock pulses for every ten clock pulses of the reference clock. Traditionally, the resolution of a counter is one full clock period. This error, of 200 nanoseconds or one clock period of the 5 MHz reference clock, in the illustration, is known to those skilled in the art as jitter. Clock signals synthesized with conventional M/N:D counters suffer from excessive clock jitter because the conventional M/N:D counter generates an output clock edge from the same point, i.e., the rollover point, in the counter sequence. As a result, output clock jitter will vary from zero to the period of the input reference clock, because the ideal output clock edge will always exist somewhere between the last clock edge of the counter period and the rollover clock edge.
Unfortunately, for certain high precision applications such jitter is unacceptable. One such application is the Universal Serial Bus (USB) application. In this application, jitter is unacceptable as it interferes with a clock recovery operation. Another illustrative application is the analog to digital conversion application. For these and other applications, it is important that the M/N:D counter operate high frequencies. However, as is well known in the art, an M/N:D counter's input clock frequency range directly correlates to the amount of jitter in the output clock.
Thus, there is a need in the art for an improved M/N counter with improved jitter performance.
SUMMARY OF THE INVENTION
The need in the art is addressed by the counter of the present invention. In the illustrative embodiment, the inventive counter includes a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter.
In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of X cycles per second and output a second clock signal having a frequency of ((M/N)*X) cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N−M.
The look-ahead circuit predicts, for a present clock cycle, the rollover point for a preceding clock cycle. In the specific illustrative embodiment, the look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.
Preferably, the first counter stage is a first M/N counter. In the preferred embodiment, the second counter stage is a second M/N counter preloaded with a value of M. In the illustrative implementation, the second M/N counter includes first and second adders, a multiplexer, and an accumulator. The first adder is adapted to sum the preloaded value of M with an instantaneous output of the accumulator and the second adder is adapted to sum a preloaded value of −(N−M) with an instantaneous output of the accumulator. The outputs of the first and second adders provide first and second inputs to the multiplexer. The preloaded value of M provides a third input to the multiplexer. The most significant bit of the output of the second adder provides a control input to the multiplexer. The output of the multiplexer is input to the accumulator and an output of the accumulator is provided to a comparator. Finally, the comparator outputs a signal indicating whether the output of the accumulator is between M/2 and M.
A circuit for the deglitching the outputs of the first and second stages is disclosed along with an arrangement for providing for backward compatibility with conventional clock synthesizers.
REFERENCES:
patent: 4761801 (1988-08-01), Underwood
patent: 4856035 (1989-08-01), Lewis
patent: 5023893 (1991-06-01), Leung et al.
patent: 5062126 (1991-10-01), Radys
patent: 5394106 (1995-02-01), Black et al.
Brown Charles D.
Greenhaus Bruce
Qualcomm Incorporated
Wadsworth Philip
Wambach Margaret R.
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