Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-06-14
2004-04-13
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S159000
Reexamination Certificate
active
06720810
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits (ICs). More particularly, the invention relates to methods and apparatus for reducing power dissipation in IC clock distribution networks.
BACKGROUND
Distributing clock signals on integrated circuits dissipates a significant amount of power, and the power dissipated increases with clock frequency. Dividing the clock by two, distributing the resulting half-speed clock, and equipping the IC with synchronous elements that respond to both rising and falling edges of the half-speed clock reduces the dissipated power. M. Afghahi and J. Yuan propose circuits that employ this method to reduce dissipated power in “Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits,” IEEE Journal of Solid-State Circuits, pages 1168-1170, Vol. 26, No. 8, August 1991, which is incorporated herein by reference. A number of other authors describe double-edge-triggered flip-flops, including Stephen H. Unger in “Double-Edge-Triggered Flip-Flops,” IEEE Transactions on Computers, Vol. C-30, No. 6, pages 447-451, June 1981; and Shih-Lien Lu and Milos Ercegovac in “A Novel CMOS Implementation of Double-Edge-Triggered Flip-Flops,” IEEE Journal of Solid-State Circuits, Vol. 25, No. 4, August 1990, pages 1008-1010; both of which are incorporated herein by reference.
FIG. 1
, taken from U.S. Pat. No. 6,072,348 to New et al., shows a clock distribution circuit
100
for an FPGA in which the frequency of an incoming reference clock signal CK is optionally divided by two and distributed at the new, lower frequency to reduce power consumption. The clock distribution circuit comprises a programmable clock divider
101
, a clock distribution network
103
, and a programmable double-edge flip-flop
105
. Flip-flop
105
is typically one of many clock destinations on clock distribution network
103
. The above-mentioned patent to New et al. is incorporated herein by reference.
Clock divider
101
includes a single-edge flip-flop
110
, a multiplexer
115
, and an inverter
120
. Flip-flop
110
and multiplexer
115
each receive clock signal CK. The output of flip-flop
110
feeds back through inverter
120
to the data input D of flip-flop
110
, thereby forming a clock divider that divides the clock frequency of clock signal CK by two. The output of flip-flop
110
also drives one input of multiplexer
115
. A configurable memory cell
125
selects one or the other input of multiplexer
115
, and consequently provides a global clock signal GCK with either the same frequency as clock CK (when multiplexer
115
selects clock line CK) or one-half of that frequency (when multiplexer
115
selects the output of flip-flop
110
). Clock distribution network
103
distributes global clock signal GCK to a number of other programmable flip-flops, including flip-flop
105
.
Each programmable flip-flop includes a configuration memory cell
130
. The bit stored in configuration memory cell
130
(i.e., a logic one or a logic zero) determines whether the associated flip-flop exhibits either single-edge or double-edge functionality. A single memory cell
130
can control more than one flip-flop.
A problem encountered with the scheme of
FIG. 1
is that clock distribution network
103
may exhibit different propagation delays for falling and rising edges, due to unbalanced driver circuits, for example. Synchronous logic elements (e.g., flip-flop
105
) may therefore have more or less time to settle in alternate half cycles of the distributed clock. To ensure proper operation, the synchronous elements should settle in the shorter half cycle: the additional time in the longer half cycle is wasted, reducing speed performance.
SUMMARY
The invention provides a clock distribution circuit and method in which the incoming clock frequency is divided by two to create a reduced-frequency global clock signal. A dual-edge-correcting clock synchronization circuit (e.g., a delay-locked loop) aligns both the rising and falling edges of the global clock signal to separately nullify the clock-distribution delays associated with rising and falling clock edges. The resulting improvement in clock accuracy facilitates greater clock speeds, and consequently improves speed performance.
This summary does not limit the invention, which is instead defined by the claims.
REFERENCES:
patent: 4604582 (1986-08-01), Strenkowski et al.
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5428309 (1995-06-01), Yamauchi et al.
patent: 5815016 (1998-09-01), Erickson
patent: 5828257 (1998-10-01), Masleid
patent: 5838179 (1998-11-01), Schmidt
patent: 5999025 (1999-12-01), New
patent: 6072347 (2000-06-01), Sim
patent: 6072348 (2000-06-01), New et al.
patent: 6184733 (2001-02-01), Wang et al.
patent: 6191613 (2001-02-01), Schultz et al.
patent: 6289068 (2001-09-01), Hassoun et al.
patent: 6373308 (2002-04-01), Nguyen
Shih-Lien Lu, Milos Ercegovac; “A Novel CMOS Implementation of Double-Edge-Triggered Flip-Flops”; IEEE Journal of Solid-State Circuits, vol. 25, No. 4; Aug. 1990; pp. 1008-1010.
M. Afghahi, J. Yuan; “Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits”; IEEE Journal of Solid-State Circuits, vol. 26, No. 8; Aug. 1991; pp. 1168-1170.
Stephen H. Unger; “Double-Edge-Triggered Flip-Flops”; IEEE Transactions on Computers, vol. C-30, No. 6; Jun. 1981; pp. 447-451.
Behiel Arthur J.
Lam Tuan T.
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