Dual dynamic sense amplifiers for a memory array

Details Dual dynamic sense amplifiers for a memory array Dual dynamic sense amplifiers for a memory array

1992-12-22

1995-10-03

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365207, 36518905, 365190, 365202, 326 51, 326 57, G11C 1134

Patent

active

054558026

ABSTRACT:
A method and circuit for reading a memory array by utilizing dual dynamic sense amplifiers. A first and a second dynamic sense amplifier are connected to an input line and complementary input line. A latch and a clocking circuit are also connected to the two dynamic sense amplifiers. Initially, an equilibrating signal is input into both sense amplifiers. A first clocking signal and a first isolating signal are then input into the first dynamic sense amplifier. The first clocking signal enables the first sense amplifier to read the data on the input and complementary input lines, while the first isolating signal isolates the first sense amplifier from the input and complementary input lines. An output is then provided to the latch based upon the data read by the first sense amplifier. A second clocking signal and a second isolating signal are then input into the second sense amplifier to enable the second sense amplifier to read the data on the input and complementary input lines. The state of the latch may or may not change based upon the data read by the second sense amplifier.

REFERENCES:
patent: 5023841 (1991-06-01), Akrout et al.
patent: 5220527 (1993-06-01), Ohsawa
patent: 5291452 (1994-01-01), Hotta

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