Dual domino CMOS logic circuit, including complementary vectoriz

Details Dual domino CMOS logic circuit, including complementary vectoriz Dual domino CMOS logic circuit, including complementary vectoriz

1986-08-26

1987-12-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307471, 307481, 307269, H03K 19003, H03K 19096

Patent

active

047106506

ABSTRACT:
At each stage of a domino CMOS logic circuit, the output signal S and its inversion S are separately generated in mutually complementary first and second logic networks. These outputs S and S are then used as inputs for succeeding domino logic stages. In this way, both S and S are guaranteed to be low at the end of the precharging phase as is desired for inputs to all domino logic.

REFERENCES:
patent: 3953743 (1976-04-01), Hollingsworth
patent: 4049974 (1977-09-01), Boone et al.
patent: 4367420 (1983-01-01), Foss et al.
patent: 4575648 (1986-03-01), Lee
Cole et al., "Logic Gate", IBM T.D.B., vol. 16, No. 2, Jul. 1973, p. 566.
Ho et al., "Static Shift Register for FET Technology", IBM T.D.B., vol. 13, No. 6, Nov. 1970, pp. 1450-1451.
"Latched Domino CMOS Logic", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 4, Aug. 1986, pp. 514-522.

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