Dual direction integrating delay circuit

Details Dual direction integrating delay circuit Dual direction integrating delay circuit

1988-07-13

1989-03-14

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307605, 307290, 307263, 307265, 323316, H03K 513, H03K 329, G05F 316

Patent

active

048126870

ABSTRACT:
A CMOS circuit that provides an output pulse having rising and falling edges that are delayed by predetermined different amounts from the rising and falling edges of an input pulse.

REFERENCES:
patent: 3473050 (1969-10-01), Groom
patent: 3571626 (1971-03-01), Reif
patent: 3906247 (1975-09-01), Heffner
patent: 3985970 (1976-10-01), Lerault et al.
patent: 4503345 (1985-03-01), Yamamura
patent: 4580065 (1986-04-01), Hague
patent: 4620312 (1986-10-01), Yamashita
patent: 4675546 (1987-06-01), Shaw
patent: 4717843 (1988-01-01), Yoshimura

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