Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2002-03-26
2003-09-09
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S012000, C327S067000
Reexamination Certificate
active
06617883
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for phase detection generally and, more particularly, to a method and/or architecture for dual differential input comparators with an integrated phase detector.
BACKGROUND OF THE INVENTION
Certain applications use an output signal that indicates as accurately as possible which of two differential signals arrives first. The arrival of the signal can be determined by a rising edge of the signal. The rising edge of a differential signal can be defined as the time when the positive differential input rises to an amplitude more positive than the negative differential input. In general, the determination of arrival time is referred to as phase detection with the earlier signal said to be ahead or leading in phase. A digital or binary phase detector indicates only which signal is ahead and does not quantify the amount by which one signal leads the other signal.
Referring to
FIG. 1
, a block diagram of a conventional phase detector
10
is shown. The phase detector
10
includes a comparator
20
, a comparator
22
, a NAND gate
24
, a NAND gate
26
, and inverting buffers
28
and
30
. The comparator
20
receives a differential signal CLK1 (i.e., the signals CLK1+ and CLK1−). The comparator
22
receives a differential signal CLK2 (i.e., the signals CLK2+ and CLK2−). The comparators
20
and
22
amplify the differential signals CLK1 and CLK2 to generate full swing logic level outputs A
1
and A
2
, respectively. For example, the differential signals CLK1 and CLK2 can be positive emitter coupled logic (PECL) signals that swing +/−250 mV around 2.0V. The 500 mV voltage swing of the signals CLK1 and CLK2 is amplified to a 0-VDD CMOS logic level by the comparators
20
and
22
. The technique can be applied to other signal levels and even single ended signals where the negative inputs of the comparators
20
and
22
(i.e., CLK1− and CLK2−) are connected to a DC reference voltage. The differential signals CLK1 and CLK2 can have levels that swing from rail to rail.
An input rising edge of the differential signal CLK1 is defined when the signal CLK1+ rises to a more positive potential than the signal CLK1−. After some delay, the output A
1
of the comparator
20
rises from 0 to VDD. The output A
2
of the comparator
22
responds similarly when the signal CLK2+ rises to a more positive potential than the signal CLK2 −.
The NAND gates
24
and
26
perform the phase comparison operation on the full swing logic signals A
1
and A
2
. While A
1
and A
2
are below a logic threshold of the gates
24
and
26
(e.g.; a logic LOW), outputs B
1
and B
2
of the gates
24
and
26
, respectively, are HIGH (e.g., a logic “1”) and signals CLK1LEAD and CLK2LEAD are both LOW (e.g., a logic “0”). When the signal A
1
rises before the signal A
2
, the output of the gate
24
(i.e., the signal B
1
) transitions LOW when the signal A
1
reaches the logic threshold of the gate
24
. The threshold of the gate
24
is typically VDD/2. When the signal B
1
becomes LOW, the signal B
2
is forced to remain LOW even after the signal A
2
rises. The signal CLK1LEAD transitions HIGH and the signal CLK2LEAD remains LOW. The signal CLK1LEAD can be sampled by other digital circuitry and processed.
A disadvantage of the circuit
10
is that the differential signals CLK1 and CLK2 are amplified to full swing logic levels in order for the cross coupled gates
24
and
26
to make a decision on which signal arrived first. In addition, each of the comparators
20
and
22
can add a delay that is proportional to the following factors: the amplitude of the respective differential input signal; the slew rate of the respective differential input signal; and the load capacitance the comparator must drive. The sensitivity of the comparator delays to input signal amplitude and slew rate can increase (i) the more the signal is amplified and (ii) the greater the load capacitance the comparator must drive.
Referring to
FIG. 2
, a timing diagram illustrating various signals of
FIG. 1
is shown. A timing error “&Dgr;TERR” can be defined as the input arrival time difference between the signals CLK1 and CLK2 that results in the two signals A
1
and A
2
arriving simultaneously at the inputs of the cross coupled gates
24
and
26
(e.g., the point
32
). The signals CLK1LEAD and CLK2LEAD each have a 50% chance of transitioning HIGH or LOW. When the slew rate of the signal CLK1 is lower than the slew rate of the signal CLK2, the amplified output of the comparator
20
can rise more slowly than the output of the comparator
22
. When the output of the comparator
20
rises more slowly than the output of the comparator
22
. The signal CLK1 must arrive earlier than the signal CLK2 for the signals A
1
and A
2
to arrive at the comparison gates
24
and
26
at the same time. The arrival time difference is the timing error &Dgr;TERR.
The timing error &Dgr;TERR can be minimized by minimizing the switching range of the inputs of the comparators
20
and
22
(i.e., making the DC gain of the comparators as large as possible). High DC gain can be obtained with high transconductance (GM) transistors in the front end of the comparators
20
and
22
. High GM CMOs transistors are physically large and run at small current density. Large input transistors and small current density have disadvantages including: (i) larger parasitic gate to drain and gate to source capacitance; (ii) larger input capacitance; (iii) greater power consumption; and (iv) greater layout area requirement.
The above factors can impose practical limitations on the gain of the comparators
20
and
22
. The input capacitance of the comparators
20
and
22
can become large. The physical area used for the comparators
20
and
22
can become large. The speed of the circuit
10
can decrease due to increases in parasitic loading. For example, larger parasitic capacitance can cause parasitic signal paths (e.g., gate-drain and gate-source capacitance) that add another mechanism for the delay of the comparators
20
and
22
to change with input signal slew rate and amplitude.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first intermediate signal in response to a first differential signal and to generate a second intermediate signal in response to a second differential signal. The second circuit may be configured (i) to generate one or more output signals in response to a relative arrival time of the first and second intermediate signals and (ii) to clamp a later arriving one of the first and second intermediate signals to a predefined voltage level.
The objects, features and advantages of the present invention include providing dual differential input comparators with an integrated phase detector that may (i) accurately detect which of two signals arrives first; (ii) minimize timing error in detecting which signal arrives first when the two signals have different rise times (slew rates) and or amplitudes; (iii) minimize timing error in detecting which signal arrives first by minimizing the voltage swing required of an input amplifier; (iv) comprise a pair of cross-couple transistors; (v) be integrated with a differential amplifier; (vi) replace the functionality of a pair of cross-coupled logic gates; (vii) make the decision of which signal arrives first at a very small voltage change; and/or (viii) present a minimum load to the comparators maximizing their speed.
REFERENCES:
patent: 5691656 (1997-11-01), Sandusky
Pickering, US Patent Application Publication 2002/0, 125, 960.*
Sedra et al., “Microelectronic Circuits,” CBS College Publishing, second edition, pp. 867-878.*
Kuhn, Jay A., “Circuit for Correction of Differential Signal Path Delays in a PLL”, U.S. Ser. No. 09/846,146, filed Apr. 30, 2001.
Kuhn, Jay A., “Master/Dual-Slave D Type Flip-Flop”, U.S. Ser. No. 09/844,785, filed Apr. 27, 2001.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Tran Toan
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