Dual differential comparator with weak equalization and narrow m

Details Dual differential comparator with weak equalization and narrow m Dual differential comparator with weak equalization and narrow m

1997-10-22

1999-06-15

Butler, Dennis M.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 91, 395559, G11C 2702

Patent

active

059125675

ABSTRACT:
In a sample-and-hold circuit, an input is tracked at an output during a tracking period and the input is held during an holding period, the tracking period and holding period defined by a clock signal input to the sample-and-hold circuit, wherein the output is a differential output having a positive output node and a negative output node with the output signal represented by a voltage difference from the negative output node to the positive output node. During the tracking period, an equalizing transistor between the output nodes is turned on to bring the output to a common mode level for the output. During the holding period, the equalizing transistor is turned off and a regenerative circuit drives the output nodes apart, thus amplifying the input signal.

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B. Razavi, "Principles of Data Conversion System Design", IEEE Press, (1995), Chapter 2, pp. 7-27.
A. Fiedler, et al., "A 1.0625Gbps Transceiver With 2x-Oversampling and Transmit Signal Pre-Emphasis", 1997 IEEE International Solid State Circuits Conference, Session 15, Serial Data Communications, Paper FP 15.1, pp. 238-239.
Chih-Kong Ken Yang, et al. "A 0.8-.mu.m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links", IEEE Journal of Solid State Circuits, vil. 31, No. 12, Dec. 1996, pp. 2015-2023.

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