Dual differential and binary data transmission arrangement

Details Dual differential and binary data transmission arrangement Dual differential and binary data transmission arrangement

1993-12-10

1998-04-14

Bocure, Tesfaldet

Pulse or digital communications

Multilevel

375259, 341 56, H04L 2534, H04L 2549

Patent

active

057402019

ABSTRACT:
Data transmission arrangement for transmitting data between integrated circuit chips in a computer comprises a driver circuit having inputs connected to two discrete data bits. The driver circuit converts the states of the two data bits to one of four possible output voltage levels on each of two data transmission conductors. A receiver circuit connected to the data transmission conductors converge the multi-level signals on the pair of transmission conductors into binary output signals for use in a receiving circuit chip. The driver circuit and receiver circuit are balanced circuits and symmetrically arranged such that essentially the same magnitude of current is drawn from the power bus independent of the value of the signal being transmitted, thereby eliminating Delta-I noise typically occurring on a power bus when binary data is transmitted.

REFERENCES:
patent: 3508076 (1970-04-01), Winder
patent: 3638122 (1972-01-01), Gibson
patent: 4373152 (1983-02-01), Jacobsthal
patent: 4528550 (1985-07-01), Graves et al.
patent: 4631428 (1986-12-01), Grimes
patent: 4730266 (1988-03-01), van Meerbergen et al.
patent: 4740907 (1988-04-01), Shimizu et al.
patent: 4916653 (1990-04-01), Shimizu et al.
patent: 5259002 (1993-11-01), Carlstedt

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