Dual differential and binary data receiver arrangement

Details Dual differential and binary data receiver arrangement Dual differential and binary data receiver arrangement

1997-06-02

1999-02-16

Chin, Stephen

Pulse or digital communications

Multilevel

375257, H04L 2534, H04L 2549

Patent

active

058728139

ABSTRACT:
Data transmission arrangement for transmitting data between integrated circuit chips in a computer comprises a driver circuit having inputs connected to two discrete data bits. The driver circuit converts the states of the two data bits to one of four possible output voltage levels on each of two data transmission conductors. A receiver circuit connected to the data transmission conductors converge the multi-level signals on the pair of transmission conductors into binary output signals for use in a receiving circuit chip. The driver circuit and receiver circuit are balanced circuits and symmetrically arranged such that essentially the same magnitude of current is drawn from the power bus independent of the value of the signal being transmitted, thereby eliminating Delta-I noise typically occurring on a power bus when binary data is transmitted.

REFERENCES:
patent: 4373152 (1983-02-01), Jacobsthal
patent: 4606046 (1986-08-01), Ludwick
patent: 4888764 (1989-12-01), Haug
patent: 5444740 (1995-08-01), Mizukami et al.
patent: 5684833 (1997-11-01), Watenabe
patent: 5740201 (1998-04-01), Hui

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