Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2001-03-01
2002-06-04
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S107000, C438S111000, C438S123000
Reexamination Certificate
active
06399421
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor die packaging, and more particularly to a dual-dies packaging structure, and a packaging method.
2. Description of Related Art
As a device integration continuously increases, a more efficient packaging structure of dies is also desired by manufacturers. In order to more effectively use an available space, two dies may be packaged together in an integrated circuit (IC) chip, in which these two dies may have either similar function or different function. Thus, the dual-dies IC chip can have a greater capability or more various functions. However, it is difficult to achieve this kind of dual-dies packaging structure.
When two dies are to be packaged together, these two dies usually are respectively mounted on both sides of a lead frame. If these two dies have an identical circuit layout, such as two dynamic random access memory (DRAM) dies to increase memory capacity, those bonding wires between bonding pads and the lead frame inevitably need to cross to each other or even entangle together. In order to avoid this issue, several dual-dies packaging structures are proposed.
FIG. 1
is a cross-sectional view of an IC chip, schematically illustrating a conventional dual-dies packaging structure. In
FIG. 1
, an usual dual-dies packaging structure includes a die pad
14
, which is horizontally set. A die
12
is fixed on an upper surface of the die pad
14
, and a die
16
is fixed on a lower surface of the die pad
14
. The die
16
is a mirror die with respect to the die
12
so that bonding wires
10
are not necessarily crossed to each other. In this conventional manner, the circuit layout of the die
16
is necessary to be extra designed to fit its mirror structure with respect to the die
12
. This increases fabrication time and fabrication cost.
FIG. 2
is a cross-sectional view of an IC chip, schematically illustrating an another conventional dual-dies packaging structure. In
FIG. 2
, a die pad
33
is horizontally set in a space. According to the geometry location of the die pad
33
, the die pad
33
includes an additional circuit, called an interposer
36
, located on a lower surface of the die pad
33
. An usual die
32
is fixed on an upper surface of the die pad
33
, a die
34
, identical to the die
32
, is fixed on a lower surface of the die pad
33
. The interposer
36
is used to convert bonding pad locations of the die
34
into a new locations so that bonding wires
30
for the die
34
need not cross each other. This conventional method has it limitation. If a die dimension is large and occupies most of the area of the die pad
33
, then there is no available area on the die pad
33
for forming the interposer
36
. Moreover, signal is led out through the interposer
36
, the signal may be distorted. An unequal bonding length may also cause a signal delay.
There is also another dual-dies packaging structure. A die pad is replaced by a printed circuit board. Through a layout of the printed circuit board, signals of dies can be led out. This method also has it drawbacks. Since the material of the printed circuit board and the packaging glue have a poor glue performance. This cause an increase of fabrication cost to obtain a sufficient glue strength. Moreover, the signals may also distorted.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a dual-dies packaging structure, which makes use of a bumping redistribution method to relocate bonding pad location so that the relocated bonding pad pattern has a match with an usual bonding pad pattern. The dies therefore can be easily and symmetrically bonded out through bonding wires. A signal delay is also avoided.
It is another an objective of the present invention to provide a more efficient packaging method to package dual-dies so that dual-dies simply packaged with a lower fabrication cost and a lower fabrication time.
In accordance with the foregoing and other objectives of the present invention, a dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes a first surface and a second surface. A first die with several first bonding pads is fixed on the first surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the second surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other. All this coupling structure described above is firmly sealed by a packaging glue material, such as resin. When the dual-dies packaging structure is done, some other packaging processes are performed to accomplish an IC chip.
In the foregoing, in accordance with the above objective and other objectives of the present invention, a dual-dies packaging method is also provided. The dual-dies packaging method includes fixing a first die on one surface of a die pad, that is, a first surface of the die pad. The die pad is a part of a lead frame, which further includes several lead legs. The first die includes several first bonding pads, which are exposed. Using a bumping redistribution method to form a bumping redistribution structure layer on the second die to redistribute its second bonding pads forms several pseudo-bonding pads on the second die. The second die is fixed by, for example, glue on a second surface of the die pad, which is opposite to the first surface. The pseudo-bonding pads have proper relative locations to the first bonding pad of the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other. A packaging glue/firm process is performed to seal the first die, the second die, the die pad, the bonding wire, and the bumping redistribution structure layer and form a firmed IC chip.
REFERENCES:
patent: 5366933 (1994-11-01), Golwalkar et al.
patent: 5527740 (1996-06-01), Golwalkar et al.
patent: 5915169 (1999-06-01), Heo
patent: 6043109 (2000-03-01), Yang et al.
patent: 6072243 (2000-06-01), Nakanishi
patent: 6133067 (2000-10-01), Jeng et al.
Han Charlie
Yang Te-Sheng
Picardat Kevin M.
United Microelectronics Corp.
LandOfFree
Dual-dies packaging structure and packaging method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual-dies packaging structure and packaging method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual-dies packaging structure and packaging method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2958775