Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-10-10
2002-11-05
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S646000, C257S693000, C257S493000, C257S723000, C257S777000, C257S784000, C257S786000, C257S676000
Reexamination Certificate
active
06476474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a duel-due package structure and method of fabricating the same, which is characterized in the use of a face-to-face stacked dual-die construction to pack two integrated circuit chips in one single package module.
2. Description of Related Art
Integrated circuit chips are typically enclosed in protective packages that can be easily handled and mounted onto printed circuit boards (PCB). A single package can be used to enclose one or more integrated circuit chips therein.
Dual-die packaging technology is used to pack two integrated circuit chips in one single package module, so that one single package module is capable of offering a double level of functionality or data storage capacity. Memory chips, such as flash memory chips, are typically packaged in this way so as to allow one single memory module to offer a doubled level of data storage capacity. Conventionally, various kinds of dual-die packaging technologies have been developed and utilized in the semiconductor industry, such as the one illustrated in FIG.
1
.
As shown in
FIG. 1
, this conventional dual-die package structure comprises a first semiconductor die
10
, a second semiconductor die
20
, and a leadframe
30
. The first semiconductor die
10
has a circuit surface (or called active surface)
10
a
and a non-circuit surface (or called inactive surface)
10
b
, and is formed with a lined array of bond pads
11
on one edge of the circuit surface
10
a
thereof (only one bond pad is shown in the schematic sectional diagram of FIG.
1
). Similarly, the second semiconductor die
20
has a circuit surface
20
a
and a non-circuit surface
20
b
, and is formed with a lined array of bond pads
21
on one edge of the circuit surface
20
a
thereof (only one bond pad is shown in the schematic sectional diagram of FIG.
1
). The first semiconductor die
10
and the second semiconductor die
20
can be each a memory chip, such as a flash memory chip. Besides, they can also be various other kinds of integrated circuit chips, such as microcontroller chips.
The leadframe
30
includes a first set of conductive leads
31
, a second set of conductive leads
32
, and a die pad
33
. The two sets of conductive leads
31
,
32
are arranged on opposite sides of the die pad
33
. The first set of conductive leads
31
have a front side
31
a
and a back side
31
b
, and the second set of conductive leads
32
have a front side
32
a
and a back side
32
b
. The die pad
33
has a front side
33
a
and a back side
33
b
, and which is arranged at a leveled position with respect to the two sets of conductive leads
31
,
32
. The first semiconductor die
10
has its non-circuit surface
10
b
securely attached by means of a first adhesive layer
12
to the front side
33
a
of the die pad
33
, while the second semiconductor die
20
has its non-circuit surface
20
b
securely attached by means of a second adhesive layer
22
to the back side
33
b
of the die pad
33
.
Further, a first set of bonding wires
41
are interconnected between the bond pads
11
of the first semiconductor die
10
and the front side
31
a
of the first set of conductive leads
31
for electrically coupling the first semiconductor die
10
to the first set of conductive leads
31
; and a second set of bonding wires
42
are interconnected between the bond pads
21
of the second semiconductor die
20
and the back side
32
b
of the second set of conductive leads
32
for electrically coupling the second semiconductor die
20
to the second set of conductive leads
32
. After this, an encapsulation process is performed to form a molded compound
50
for encapsulating the first semiconductor die
10
and the second semiconductor die
20
.
The foregoing dual-die package structure is one example of the prior art. Other related patents include, for example, the U.S. Pat. No. 5,814,881 entitled “STACKED INTEGRATED CHIP PACKAGE AND METHOD OF MAKING SAME”. This patented technology is characterized in the use of a back-to-back stacked dual-die construction on one side of the die pad of leadframe for packing two integrated circuit chips in one single package module.
SUMMARY OF THE INVENTION
It is an objective of this invention to provide a new dual-die packaging technology which can be used to pack two integrated circuit chips in one single package module.
In accordance with the foregoing and other objectives, the invention proposes a new dual-die packaging technology for packing two integrated circuit chips in one single package module.
In terms of package structure, the dual-die packaging technology of the invention comprises: (a) a leadframe including a die pad, a first set of conductive leads on side of the die pad, and a second set of conductive leads on opposite sides of the die pad; the fist set of conductive leads and the second set of conductive leads each having a front side and a back side; (b) a first semiconductor die having a circuit surface and a non-circuit surface and including an array of bond pads on one edge of the circuit surface thereof, and whose non-circuit surface is attached to the die pad of the leadframe; (c) a second semiconductor die having a circuit surface and a non-circuit surface and including an array of bond pads on one edge of the circuit surface thereof, and whose circuit surface is attached to the circuit surface of the first semiconductor die; (d) a first set of bonding wires for electrically connecting the bond pads of the first semiconductor die to the front side of the first set of conductive leads of the leadframe; (e) a second set of bonding wires for electrically connecting the bond pads of the second semiconductor die to the back side of the second set of conductive leads of the leadframe; and (f) a molded compound for encapsulating the first semiconductor die and the second semiconductor die.
In terms of fabrication method, the dual-die packaging technology of the invention comprises the following steps of: (1) preparing a first semiconductor die, a second semiconductor die, and a leadframe; the leadframe including a die pad, a first set of conductive leads on side of the die pad, and a second set of conductive leads on opposite side of the die pad; the first set of conductive leads and the second set of conductive leads each having a front side and a back side; and the first semiconductor die and the second semiconductor die each having a circuit surface and a non-circuit surface and including an array of bond pads on one edge of the circuit surface thereof; (2) performing a first die-bonding process, wherein the non-circuit surface of the first semiconductor die is attached to the front side of the die pad of the leadframe; (3) performing a second die-bonding process, wherein the circuit surface of the second semiconductor die is attached to the circuit surface of the first semiconductor die; (4) performing a first wire-bonding process to electrically connect the bond pads of the first semiconductor die to the front side of the first set of conductive leads of the leadframe; (5) performing a second wire-bonding process to electrically connect the bond pads of the second semiconductor die to the back side of the second set of conductive leads of the leadframe; and (6) performing an encapsulation process to form a molded compound for encapsulating the first semiconductor die and the second semiconductor die.
The foregoing dual-die packaging technology of the invention is characterized in the use of a face-to-face stacked dual-die construction, which is distinguishable from the back-to-back stacked dual-die construction of the prior art, for packing two semiconductor chips in one single package module, so that the one single package module is capable of offering a doubled level of functionality or data storage capacity.
REFERENCES:
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5777345 (1998-07-01), Loder et al.
patent: 5780925 (1998-07-01), Cipolla et al.
patent: 58148
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
Williams Alexander O.
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