Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-04-18
2003-07-15
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S635000, C257S640000
Reexamination Certificate
active
06593659
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and more particularly, to a semiconductor device with the dual damascene structure in which the wire-to-wire capacitance is reduced and the propagation delay of signals is suppressed, and a method of fabricating the device without using any complicated process steps.
2. Description of the Prior Art
In recent years, there has been the increasing need to raise the speed of signal processing in semiconductor devices, especially in Large-Scale Integrated circuits (LSIs). The signal processing speed in LSIs is mainly dependent upon the operation speed of individual transistors and the delay of signals propagating through wiring lines.
Conventionally, the operation speed of transistors has been gradually raised according to their consecutive dimensional reduction. However, in LSIs fabricated under the design rule of 0.18 &mgr;m or less, it has been found that the signal processing speed is affected more by the propagation delay of signals in wiring lines than by the operation speed of transistors.
To reduce the propagation delay of signals, vigorous development has been made to intend the use of copper (Cu) instead of aluminum (Al), because Cu is lower in electric resistance than Al. Since Cu is lower in vapor pressure than that of halides, it is difficult to be processed or patterned by ordinary dry etching processes at low temperatures. Thus, it is usual that wiring recesses are formed in a silicon dioxide (SiO
2
) layer and then, Cu is deposited on the SiO
2
layer to fill the recesses with Cu, thereby forming wiring lines made of Cu in the recess. These Cu wiring lines constitute a Cu wiring layer.
The wiring structure thus formed is termed the “damascene structure”. If the Cu wiring lines are simply formed in the recesses, the process is termed the “single damascene process”. If the Cu wiring lines are formed in the recesses and at the same time, via holes for interconnecting the Cu wiring layer with an underlying wiring layer or underlying electronic elements are formed, the process is termed the “dual damascene process”. Considering the fabrication cost of LSIs, the dual damascene process is preferred to the single one.
FIGS. 1A
to
1
D show an example of the prior-art methods of fabricating an LSI using the dual damascene process.
First, as shown in
FIG. 1A
, a SiO
2
layer
302
is formed on the surface of a single-crystal silicon substrate
301
as a first interlayer dielectric layer. Although the substrate
301
has specific electronic elements such as transistors and at least one wiring layer connected thereto, only a diffusion region
301
a
of one of the elements is illustrated in
FIG. 1A
for the sake of simplification.
A silicon nitride (SiN
x
) layer
303
is then formed on the SiO
2
layer
302
serving as the first interlayer dielectric layer. The SiN
x
layer
303
serves as a second interlayer dielectric layer. The SiN
x
layer
303
is patterned by using a patterned photoresist film (not shown) to form an opening
303
a
exposing the surface of the underlying SiO
2
layer
302
. The opening
303
a
is located to overlap with the underlying diffusion region
301
a
of the substrate
301
. The opening
303
a
forms an upper part of a desired via hole to be formed in the subsequent process steps.
Although any other openings are formed in the layer
303
, only one of them is shown here for simplicity. The state at this stage is shown in FIG.
1
A.
Subsequently, as shown in
FIG. 1B
, a SiO
2
layer
304
is formed on the SiN
x
layer
303
to cover the whole substrate
1
as a third interlayer dielectric layer. The opening
303
a
is filled with the layer
303
. Then, a patterned photoresist film
305
is formed on the SiO
2
layer
304
. The photoresist film
305
has a pattern corresponding to that of a desired wiring layer. Only a window
305
a
or the film
305
is shown in
FIG. 1B
for simplicity.
Using the patterned photoresist film
305
as a mask, the SiO
2
layer
304
is selectively etched by an ordinary dry etching process to form a wiring recess
311
in the layer
304
, as shown in FIG.
1
C. The recess
311
extends on the SiN
x
layer
303
from back to forth in a direction perpendicular to the paper. During the same etching process, the underlying SiO
2
layer
302
is selectively etched while the SiN
x
layer
303
with the opening
303
a
is used as a mask, thereby forming an opening
302
a
in the layer
302
. The openings
302
a
and
303
a
, which are overlapped with each other and communicate therewith, constitute a via hole
312
interconnecting the recess
311
with the diffusion region
301
a
of the substrate
301
. Thereafter, the photoresist film
305
is removed. The state at this stage is shown in FIG.
1
C.
During the above-described etching process, the SiN
x
layer
303
serves as an etch stop layer for the SiO
2
layer
302
and a masking layer therefor. Therefore, the SiO
2
layer
302
can be selectively etched as explained above, resulting in the dual damascene structure, as shown in FIG.
1
C.
A barrier layer
306
, which is made of a metal such as tantalum (Ta) and titanium nitride (TiN), is formed to cover the exposed surfaces of the recess
311
and the via hole
312
and the diffusion region
301
a
, as shown in FIG.
1
D.
A Cu plug
307
is then formed on the barrier layer
306
in the via hole
312
, and a Cu wiring layer
308
is formed on the barrier layer
306
in the recess
311
so as to be contacted with the plug
307
, as shown in FIG.
1
D. The Cu plug
307
and the CU wiring layer
308
are formed by depositing a Cu layer to cover the entire SiO
2
layer
304
using a plating, sputtering, or Chemical Vapor Deposition (CVD) process, and by selectively removing the Cu layer thus deposited by a Chemical Mechanical Polishing (CMP) process.
Finally, a SiN
x
layer
309
is formed on the SiO
2
layer
304
to cover the Cu wiring layer
308
. The layer
309
serves as a fourth interlayer dielectric layer and a diffusion prevention layer of Cu existing in the wiring layer
308
.
However, the prior-art method shown in
FIGS. 1A
to
1
D has the following problem.
Since the SiN
x
layer
303
, which has a relative dielectric constant as high as approximately 7 to 8, is used as an etch stop layer during the etching process of the SiO
2
layers
304
and
302
, the wire-to-wire capacitance becomes extremely higher than the ease where the SiN
x
layer
303
is replaced with a SiO
2
layer due to the fringing field effect. This increases largely the propagation delay of signals.
The same problem as above will occur if the SiN
x
layer
303
is replaced with a silicon oxynitride (SiON) layer having a relative dielectric constant of approximately 5 to 6.
To solve the above-described problem, improved methods have been developed, in which an organic dielectric layer is used as an interlayer dielectric layer rather than a SiN
x
layer. The organic dielectric layer is made of, for example, a polytetrafluoroethylene (PTFE), a fluorinated polyallyl ether, or a fluorinated polyimide. These improved methods are disclosed in the Japanese Non-Examined Patent Publication Nos. 10-112503 published in April 1998 and 10-150105 published in June 1998.
With the improved methods using the above-described organic dielectric layer, the above-described problem that the propagation delay of signals is increased can be solved, because the organic dielectric layers are considerably lower in relative dielectric constant than SiO
2
. However, these methods have other problems explained below.
Since the organic dielectric layers disclosed in the Japanese Non-Examined Patent Publication Non. 10-112503 and 10-150105 have a low heat- and plasma-resistant property, they tend to be changed in quality in the fabrication process sequence of LSIs (especially, in the dry etching process), resulting in increase of the relative dielectric constant. In other words, low relative dielectric constants of these layers ar
Lebentritt Michael S.
Nec Electronics Corporation
Smith Brad
LandOfFree
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